Design Engineer

Kai Tian

Email: ***********@*****.*** Cell: 585-***-**** Address: 6635 S Staples St, Corpus Christi, TX, 78413

Objective

Project Engineer of Electrical Engineering focusing on Digital Design (VHDL / Verilog) and Integrated Circuits Design.

Available immediately.

Research and Working Experience

Graduate Thesis : Fault-Resilient Lightweight Cryptographic Block Ciphers for Secure Embedded

Systems (have been accepted by Embedded Systems Letters, IEEE, available on December, 2014)

Use Xilinx Vivado to design the error detection circuits of the algorithm XTEA in VHDL, simulated with fault injection

methods and implemented on FPGA,

Hardware Implementation of Image Processing Algorithm Stucki Halftoning on FPGA Based on

the algorithm, use Xilinx ISE to design image processing circuits with USB interface and SRAM in VHDL and

implemented on FPGA,

Processor Designed a processor capable of executing 16-bit instructions and performing all the

arithmetic operations using Altera-Flex. Two programs were executed on the processor to verify the correctness of

the design,

Game PONG Designed a traditional 2D table tennis game PONG by using VHDL and implemented on

Altera-Flex FPGA. LCD Monitor interface and keyboard interface were developed as display and control unit.

Developed beatable AI algorithm to make this game more fun,

Full Costumed Standard Cell Library Designed a library of digital standard cells for the AMIS 0.5μm

CMOS Technology using the technology micron based rules. Used Cadence DFII for schematic capture, layout,

simulation, block level place and route; performed detail timing analysis and DRC and LVS verification,

5-bit BSR Designed a 5-bit boundary scan register (BSR) for testing various fundamental gates and

combinational circuits. Transient, DC and timing analysis of different design implementation were performed,

Design and Simulation of PID Controllers using Dominant Pole Placement,

Network-based Adaptive Synchronization Control of a class of Neural-type Neural Networks,

Honeywell Scanning and Mobility (HSM) Suzhou July 2011 September 2011

Reviewed different circuit diagrams for design reference

New product design

Tested prototype using variety of lab instruments

Teaching Assistant for Digital System I, II January 2014 May 2014

Tutored students using Quartus II to design digital circuits with VHDL and Verilog during lab hours

Advised students how to complete their designs, debugged codes and evaluated final results in their project

This project design is a Reduced Instruction Set Computer (RISC) with variety of components such as ALU, memory

blocks, register files, control unit and Central Processing Unit (CPU)

Education

Rochester Institution of Technology GPA: 3.67 / 4.0

Master of Science Electrical Engineering Dec, 2014

Relevant Courses:

Design of Digital System Electrical Design Automation Data & Computer Communication

Design for Testability Physical Implementation Computer Architecture

Embedded Control System Database System Network & Data communication

EDA Design Communication Theory Principles of Microcontroller

Nanjing University of Science and Technology

Bachelor of Science Automation Engineering May, 2012

Honors: University Scholarship, The runner-up of the school debate competition, Best debater throughout the competition

Language and Software Skills

C, C++, JAVA, VHDL, Verilog, MATLAB, Cadence, Microsoft Office, Xilinx ISE, Xilinx Vivado, Quartus II

Personality

Passionate Creative Well-organized Team-orientated Quick-learner

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