Engineer Sales

NISHA HEMNANI E-MAIL : *******.*****@*****.***

*** **** ***** **, ********, CA Phone : 408-***-****

Value Proposition

Proactive, analytical, and goal-focused professional with demonstrated skills in working with customers to ensure their success.

Ability to drive multiple projects working with cross-functional teams within the company to ensure customer issue resolution.

Excellent written and oral communication skills. Good understanding of ASIC design flow combined with excellent design and

debug skills.

Experience

Sr. Field Applications Engineer, Atrenta, San Jose, CA Jan 2014-Present

• Understand customer requirements and recommend solutions that align best with their business and technical

needs

• Present company products highlighting capabilities, competitive advantage and customer fit

• Work with customers during pre-sales tool evaluation to demonstrate tool capabilities

• Manage post-sales support to ensure successful adoption and proliferation of new products

• Interface with R&D, Sales, Marketing and Customers to drive new product development and resolve current

issues

• Train customers and new hires on Lint/DFT/CDC/Constraints/Power/Assembly products offerings

Sr. ASIC Design Engineer, AMD Inc., Sunnyvale, CA Feb 2008-Jan 2014

• Sole owner of fuse block that delivers fuses across the chip for Desktop processors and APUs.

• Maintained around 150K gates design to add new features and resolve any lint, CDC, LEC, timing violations.

• Implemented Secure Hash algorithm (SHA-1) to protect against unauthorized fuse modification/programming.

• Implemented support for AMBA AXI-4 bus structure for fuse distribution to various IPs.

• Sole owner of run-time power estimation block for HD6000 series of Radeon Products.

• Carried out design synthesis using Cadence Encounter RTL Compiler.

• Coded firmware features intended for power estimation in C.

• Worked on chip bring-up in the lab to test the PLL and ROM/GPIO features. Automated aspects of bring-up with

Python scripts.

• Trained members of different teams in AMD bring-up tools and settings.

Rocket IO Intern Xilinx Inc., San Jose, CA Jun 2007–Nov 2007

• Designed 128 bit CRC Soft IP Core for Virtex family

ASIC Intern, SanDisk Corp., Milpitas, CA Jun 2006–Dec 2006

• Corrected errors on design code through debugging using Verdi. Tested and qualified newly

released version of NCsim.

Customer Care Representative, GE Capital, New Delhi, India Jul 2004–Jun

2005

Education

MS Electrical Engineering, San Jose State University, San Jose, CA, 2007

BE Electronics Engineering, Amravati University, India, 2004

Skill Set

Languages : Verilog, C, Tcl, Perl, Python

EDA/CAD Tools : Novas Verdi, Xilinx ISE, ModelSim, Cadence NCsim, Synopsys, Design Compiler &

Cadence Encounter RTL Compiler, Cadence Virtuoso Suite

Knowledge : Digital Design, ASIC Design Flow, FPGA Technology, Computer Architecture, AXI-4 bus

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