Design Project

CURRICULUM VITAE

AKSHAY P Email: ******.****@*****.***

M.Tech in VLSI Design and Embedded Systems Contact: +91-996*******

CAREER OBJECTIVE

To work in a challenging environment that provides generous opportunity for learning, in

the field of VLSI design.

Technical Knowledge

Programming Languages : verilog, VHDL, system verilog & C.

Assembly level languages : 8085, 8086 µp, 8051 µc & msp430.

Tools : Xilinx ISE, Modelsim, NCsim, RTL compiler, SOC encounter,

Microwind, Matlab, Simulink, Keil and IAR.

Hardware FPGA tool : Virtex 5.

Operating Systems exposed: Windows XP, 7, 8 and Linux.

Education qualification

YEAR OF

INSTITUTION PERCENTAGE

QUALIFICATION

DISCIPLINE COMPLETION

VLSI Design &

EPCET, Bangalore

M.Tech Embedded 2014 72%

(VTU)

Systems

Electronics and

KVGCE Sullia, D.K

B.E communication 2012 61%

(VTU)

engineering

II PUC VMPUC,MANDYA 2007 62%

Science(PCMB)

SSRHS,

10th 2005 76%

State syllabus PANDAVAPURA

Additional course

MTP ( Module Training Program) on Front End and Back End VLSI Design at MSRSAS,

Bangalore.

Tools used

Simulation : Xilinx ISE14.4 and NCsim.

Synthesis : RTL compiler.

Physical design : SOC encounter.

Hardware FPGA tool : Virtex 5.

Language : Verilog.

Duration : 6 month.

Project & Seminar Detail

Project 1

Title: DESIGN AND IMPLEMENTATION OF POWER EFFICIENT TURBO DECODER

Description: soft-in soft-out turbo decoder (SISO) based on soft out viterbi algorithm (SOVA) is

designed and ASIC implementation is carried out, SOVA based turbo decoder is implemented

with high throughput and less complexity, using clock gating technique we reduces 24 % of the

power dissipation of the design.

Tools used:

Simulation : Xilinx ISE14.4

Synthesis : RTL compiler.

Physical design : SOC encounter.

Language Used: Verilog

Project 2

Title: LOW POWER MULTIPLIER DESIGN WITH ROW AND COLUMN BYPASSING

Description: It’s based on the simplification of the incremental adders and half adders instead of

full adders in an array multiplier, a low-power multiplier design with row and column bypassing

is designed and FPGA implementation is carried out, our multiplier design reduces 25.7% of the

power dissipation.

Tools used:

Simulation : Xilinx ISE13.1

Synthesis : RTL compiler.

Language Used: Verilog

Seminar

Title: TWO-BIT BINARY COMPARATOR USING REVERSIBLE LOGIC

Description: An optimized two-bit binary comparator based on reversible logic using Feynman,

Toffoli, TR, URG and BJN gates. Optimization of the comparator circuit is achieved on the basis

of total number of gates used in the circuit and total number of garbage outputs generated.

Strengths

Positive attitude

Commitment and Sincerity

Personal Details

: Sep 18th 1989

Date of Birth

Gender : Male

Nationality : Indian

Marital Status : Unmarried

Languages Known : English, Hindi and Kannada.

Permanent Address : S/O M.Panchalingegowda

C.P.Ed college campus

Jayanthinagar Pandavapura Tq

Mandya (D) – 571427

I hereby declare that all the details furnished above are true to the best of my knowledge.

Place: Bangalore

Date: [AKSHAY P]

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