High School Design

PRASHANTH R

No. ***, *st Cross Manjunatha layout, Near SGR College

Marathalli Extension, Bangalore 560037

+91-973******* ***************@*****.***

OBJECTIVE

Seeking a challenging position where I could realize my potential and

explore myself fully in the field, with committed and dedicated people.

TECHNICAL SKILLS

Languages

Assemble, C, C++, python, Verilog and VHDL.

Software

Arduino, Cadence EDA(Analog + Digital parts) Tool, keil uvision, proteus, Mat lab,

Modelsim SE, Xilinx ISE

Operating system

Linux, Windows 7

EDUCATION

2013-2015 M-tech [VLSI and Embedded system] with 72%, NEW HORIZON COLLEGE OF

ENGINERRING, Bangalore.

2009-2013 B.E [ECE] with 65.6%, SCT INSTITUTE OF TECHNOLOGY, Bangalore.

2007-2009 PUC with 64%, VAGDEVI VILAS PU COLLEGE, Bangalore.

2007 SSLC with 60%, TRINITY ENGLISH HIGH SCHOOL, Bangalore.

PROJECTS UNDERTAKEN IN ACADEMIC

1) Title : “Building an AMBA-AHB Compliant Memory Controller ”

The memory controller is compatible with AHB (Advanced High

Performance), our solution is to reduce Delay, Area of On chip Memory and

other parameters.

2) Title : “ARRAY MULTIPLIER using 180nm Technology”

Design of Array Multiplier using Cadence EDA Tool, which consist of Digital

part coded in Verilog for 16 bit multiplier and Analog part with Schematic

and layout of 4 bit Multiplier. Delay, power and size are calculated.

“Design of Charge pump and PFD in 180nm Technology”

3) Title :

The PFD (Phase and Frequency Detector) and Charge pump are essential

parts of PLL Device. Aim of project is to design Schematic and Layout in

Analog Cadence EDA Tool.

PERSONAL PROFILE

Name : Prashanth R

Date of Birth : October 15, 1991

Father Name : G Renugopal

English and Kannada

Languages :

DECLARATION

I hereby declare that the information furnished above is true to the best of my knowledge.

Place: Bangalore

Date: Prashanth R

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