Design Engineer High School

TEJAS A. BAVARVA

nd

Address: Date of birth: * October, 1989

B/404, Basera gold apartment, Email: ***************@*****.***

Bhidbhanjan society-5, Contact No.: +91-800*******

Sadhu vaswani road,

Rajkot, Gujarat

CAREER OBJECTIVE:

To obtain a challenging and demanding job in reputed organization that will further enhance

my skill, knowledge and abilities.

EDUCATION:

2012-14 M. E. (VLS I and EMBEDDED S ystem Design)

GTU PG School, Ahmedabad

8.99/10 CPI (aggregate)

2007-11 B. E. (Electronics and Communication)

G. H. Patel College of Engineering and Technology

Sardar Patel Universit y

Vallabh Vidh yanagar (Gujarat)

7.3/10 CPI (aggregate)

2006-07 H.S.C. (G.S.H.S.E.B.)

The V. C. Technical high School

Morbi (Gujarat)

76.00 % (aggregate)

2004-05 S.S.C. (G.S.H.S.E.B.)

The V. C. Technical high School

Morbi (Gujarat)

83.29 % (aggregate)

SKILLS:

English, Gujarati and Hindi

Languages Known:

VLSI ASIC design (Front end and back end ) and verification

Area of Interest:

Xilinx Vivado (Synthesis), HDL Companion (Linting), Xilinx ISE

Software:

Design, S ynops ys tools (Custom Designer, IC Designer, VCS tool,

DC shell), Modelsim PE Student Edition, iVerilog, Octave, HSP ICE,

PSPICE, KEIL(ARM), OrCAD (PCB Design), MATLAB, PLC,

MULT IS IM, Pinnacle, QUARTUS-II, Proteus, Minimos,

SUPREM4GS, LPC-Xpresso (ARM)

Verilog HDL, S ystem Verilog, Perl, VHDL, C, C++, Embedded C,

Programming Languages:

Ladder

design for PLC

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PROJECT EXPERIENCE:

Design of PCI-Express Data Link Layer Tx (at CDAC): (September - April, 2014)

Guide: Mr. Santosh Jagtap (Design Engineer Staff at LSI Corporation Ltd.)

In this project, I have developed all the sophisticated features of PCI-Express data link layer

transmitter and implementing all the data link layer protocols for the efficient communication. This

is the configurable IP design which can be used in latest version of PCI-Express. At the end of the

designing part, Linting and synthesis have been done successfull y.

PCI Bus (at SEER AKADEMI): (March - Ma y, 2013)

Guide: Mr. Santoshkrishna Mandapatti (Technical Assistant at SEER AKADEMI)

In this project, I have designed and s ynthesized the Verilog code for PCI bus and increased

the speed of PCI bus b y increasing the frequency using S ynopsis based tools (VCS, DC shell, IC

designer).

FIFO design, synthesis and GDS-II file creation: (March - May, 2013)

Guide: Mr. Santoshkrishna Mandapatti

In this project, I have designed, s ynthesized and created GDSII file for FIFO which is used to

make the chip or IC in foundry with IC Designer software.

Vibration sensing and monitoring system: (January - Ma y, 2011)

Guide: Dr. Bhaskar Thakkar (Associate Professor at G. H. Patel college of Engg. & Tech.)

In this project, we have explored the real time sensing vibration by accelerometer and

displaying them onto the LCD displa y (Nokia 6600) which is interfaced with CORTEX M3

microcontroller and then these all information is stored in memory card (Transcend 2GB).

PAPER PUBLICATION:

[1] T. Bavarva, “Configurable Design and Simulation of PCI-Express 3.0 Data Link Layer

Transmitter”, IJSRD – International Journal for Scientific Research & Development, Vol. 2, Issue. 3,

2014, PP. 413-416

[2] T. Bavarva, “Configurable Design and Simulation of Synchronous Retry Buffer for PCI-Express

3.0”, IJSRD – International Journal for Scientific Research & Development, Vol. 2, Issue. 4, 2014

CERTIFICATE:

M.E. Dissertation from C-DAC, Pune

AWARD AND ACHIEVEMENTS:

Stood 1st and prize awarded in “TECHNOHUNT”-SPECTRUM-10 held at ADIT-Anand

INTERESTES AND HOBBIES:

Safari Magazines

Table Tennis

Tennis

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Volley ball

Cricket

REFERENCES:

Name: Mr. Santosh Jagtap Name: Dr. Hitesh B. Shah

Position: Design Engineer Staff Position: Associate Professor

Company: LS I Corporation Ltd. College: G. H. Patel college of Engg. & Tech.

Mobile No: +91-960*******

Mobile No: +91-989*******

Email: ******.****@*****.***

Email: ****************@*****.**.**

I hereb y declare that all the information provided above is true to the best of my knowledge.

TEJAS A. BAVARVA

Date: 13th October, 2014

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