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verification Engineer

Location:
Bengaluru, KA, India
Posted:
December 01, 2014

Contact this candidate

Resume:

AKHIL S Email: *****************@*****.***

National Institute of Technology Mob: +91-949*******

Surathkal, Karnataka– 575025

Career Objective

To Contribute Best of my Knowledge, Skill and ability in the Growth of the Organization and attain

new Heights.

COURSE STREAM PERCENTAGE INSTITUTION UNIVERSITY YEAR

NITK

7.2 CGPA Surathkal NITK 2013 15

M.Tech VLSI

Electronics and Govt. Engg. Mahatma Gandhi

B.Tech Communicatio 68.5% College, Idukki University, Kerala 2008 12

n

Computer SNMHSS,

12 Science 89% Purakkad, Kerala Board of HSE 2008

th

Kerala

10th Science Group 89.3% MKAMHS, State Board of 2006

Pallana, Kerala Kerala

Academic Details

Academic Projects

Project Title Query by Humming Music Search

It is an efficient music search application using DTW

algorithm. We can search any kind of music data from a

Description

database just by humming or whistling part of a melody or

song. MATLAB is used for developing the algorithm.

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Project Title 32 bit RISC Processor Design

Designed 32 bit RICS processor, which can perform 36

Description operations including branch and jump. Coded in VERILOG and

verified using Modelsim and Xilinx.

Project Title Digital Clock IC Design

Layout level design and verification of a digital clock IC. This

Description IC can produce hours minutes and seconds. Magic VLSI layout

tool &NGspice are used for design and verification.

Technical Knowledge

• •

Programming C, C++ (Expert)

Languages • Assembly language( 89C51) (Prior Experience)

• Python

• •

HDLs Verilog, System Verilog(Currently working)

• •

Hardware Platforms Microcontrollers AT89S51

• Spartan 3E FPGA Kit

Magic VLSI Design (Expert)

IDE Used

LT Spice

Code composer studio

Windows, UNIX

OS Environment

• •

Designing Tools MATLAB (Expert),LabView

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Used • Xilinx, MODELSIM (Prior Experience)

Current Position

Intern at LSI R&D an Avago Company, Bangalore

Role: Design Verification Engineer(System Verilog)

From: 2 June 2014

Personal Skills

• Comprehensive problem solving abilities.Positive attitude

• Fast learning skill

• Able to adapt to new surroundings.

• Leadership quality

Achievements & Extra Curricular

Achieved 1st prize in district school level mathematical exhibition.

Achieved 1st prize in inter college technical quiz competition.

Personal Profile

Nationality Indian

Gender Male

Date of Birth 14th March 1991

Languages Known English,Malayalam,Hindi

Permanent Address Karthika (H), Pallana P O, Alappuzha,

Kerala, PIN : 690515

Hobbies

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• Solving puzzles& Rubik's cube

• Web Surfing

• Listening to music

• Gaming

DECLARATION

I hereby do declare that the above information’s are true, complete and correct to the best of my

knowledge and belief.

Place:

Date : Akhil S

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