Engineer Project

DASARI ARJUN VASUDEVA MURTHY

Email: ***********@*****.***,***********@*****.*** Phone: (M) +91-872*******

To work in an innovative and stimulating environment that would facilitate the maximum utilization and

application of my broad skills and expertise in making a positive difference to the organization

PROFILE AT GLANCE

Working as UI Developer in PointCross Pvt. Ltd.

A Skilled and enthusiastic VLSI-CAD professional with one year intern experience as Verification

Engineer in semiconductor/VLSI/EDA

Achieved Master Degree in VLSI-CAD after successful Bachelors degree in Electronics and

communications.

Gained good knowledge on IP verification using UVM Methodology,Functional Verification & SOC

Verification, Digital Design & Verification

Achieved real time experience working with professionals at STMicroelectronics

Acquired knowledge on performance,problem solving,procedures and regulations at

STMicroelectronics.

Excellent interpersonal skills with the ability to handle multiple tasks/projects.

TECHNICAL PROFICIENCIES

Operating Systems: LINUX Red Hat, WINDOWS

Languages: Verilog, SystemVerilog, C, C++,

PERL,HTML,JavaScript,EXTJS,Java(Basics),SQL

Methodology: UVM Methodology

Tools: Xilinx, Quartus, BSPICE, HSPICE, Magic, EMANAGER, Simvision,SVN

Bus protocols: AMBA-AXI, PCI, ST Imaging Bus Protocols

Simulators: VCS, NCSIM

PROFESSIONAL CONTOUR

PointCross.com Pvt. Ltd. (Aug ‘14– Present)

Software Engineer

UI Developer For Pharma Team Client :Roche

Developing Various Features for the particular solution

Modifications of different Webpages.

ST Microelectronics Private Limited, Greater Noida (Jul ‘12 – Jun ‘13)

Verification Engineer – Intern

Key Deliverables:

Stabilizing the Various Imaging IP's in SV -UVM Environment

Responsible for formulating Testcases for the IP's, running Regressions

Inspecting Functional Coverage and achieving 100% coverage

Reporting the functionality of IP's

Involved in formulating the Test Plan

Key Achievements:

Successfully verified more than 10 Imaging IP's

Successfully achieved 100% Functional Coverage

Wrote Testplans

Projects Handled:

Methodology of IP Quality

Location: ST Microelectronics, Greater Noida

Duration: Jul ‘12 – Jun ‘13

Environment: UVM, C/C++/Verilog

Description: Image signal processing algorithms are developed and evaluated using Reference models

before RTL implementation. After finalizing the algorithm, Reference models are used as a

golden model for the IP development. To increase the re-use of design effort, the common

bus protocols are defined for internal register and data transfers. A pool of such configurable

image signal processing IP modules are assembled together to satisfy a wide range of

complex video processing SOCs.

Key Deliverables:

Stabilizing the IP environment in UVM Methodology

Involved in developing Test cases for IP’s

Running Regressions and achieving 100% functional Coverage

Front –End Development Tool

Tools: Java Script

Description: This is an encapsulation of all the scripts required to perform basic tasks. It is developed to

provide ease to user, so that he can perform all the basic tasks required at the front end from

this software

PROJECT EXPERIENCE

#1:

Avionics: Cockpit Display using GL Studio

Location: Trident Infosal Private Limited, Benguluru

Duration: February – April 2011

Tools: GL Studio

Description: The main aim of the project is to design the electronic system using human machine

interface tool GL-Studio used in avionics Cockpit. Avionics system is used in wide

variety of different application ranging from flight control, instrument to navigation

and communication. This system can be generated using higher end graphics which

are suitable for any application in aircrafts where safety is critical.

Area of Application: Cockpit in all modern avionics.

Key Deliverables:

Involved in designing and implementing the design using GL Studio software

Accountable for analyzing, Documentation and report Presentation

#2:

Implementation PCI-CONTROLLER using Verilog

Tools: Xilinix

Language: Verilog

Description: PCI bus is a high performance 32 and 64 bit bus used as interconnect between the

highly integrated peripheral controller components. The arbiter decides on the basis

of Round-Robin technique, which Master go to the request of the bus whenever

there is a data to be transferred to particular slave or to read from the slave. It was

achieved by different mode in which Master will be working like memory read

memory write and memory I/O modes. The Woking of Master in different modes

were coded in Verilog and the simulation results were verified

#3:

Implementation of AMBA AXI

Tools: VCS

Language: System Verilog

Description: The project involves implementation of AMBA AXI using System-Verilog. In this

project, we implemented one master and three slaves

ACADEMIA

M.S (VLSI-CAD) from MCIS, Manipal University in 2013 with 8.31 CGPA

B.E (Electronics & Communications) from SCSVMV University in 2011 with 8.14 CGPA

Intermediate from Narayana Junior College in 2007 with 83.5%

X from NSM Public School in 2005 with 67.7%

Date of Birth: 18th June, 1990 Languages Known: English, Telugu, Hindi and Tamil

Reference: Available upon request

Contact this candidate