Design Project

KOKULAN MOHAN

Email : acgsd9@r.postjobfree.com,

acgsd9@r.postjobfree.com

Phone : +91-915*******

To work in an innovative and stimulating environment that would facilitate the maximum utilization and

application of my broad skills and expertise in making a positive difference to the organization

PROFILE AT GLANCE

Young, energetic and result-oriented B.E (Electronics & Communications) professional.

Demonstrated excellence in tackling the issues related to Digital Design & Verification.

Experienced professional with superior ability to motivate personnel and enhance the overall

efficiency, performance, and compliance with standard procedures and regulations

Keen ability to recognize and implement streamlined processes that reduce errors and

improve operational quality and efficiency

Excellent interpersonal and man-management skills with the ability to handle multiple

projects and motivate large cross-functional teams

Capable of delivering success in a complex project with scope for learning and challenge

TECHNICAL PROFICIENCIES

Operating Systems: LINUX Red Hat, WINDOWS

Languages: Verilog,VHDL, SystemVerilog, C

Tools: Xilinx, Quartus, Modelsim, HSPICE,Active HDL,Questasim

Bus protocols: AMBA-AXI,AHB,APB, PCI,UART,I2C,SPI,USB,PLL,Up converter,down

converter

CORE COMPETENCIES

~ Digital Design ~ Verilog ~ VHDL ~

PROJECT EXPERIENCE

#1:

Implementation PCI-CONTROLLER using Verilog

Tools: Xilinix,Modelsim

Language: Verilog

Description: PCI bus is a high performance 32 and 64 bit bus used as interconnect between the

highly integrated peripheral controller components. The arbiter decides on the basis

of Round-Robin technique, which Master go to the request of the bus whenever

there is a data to be transferred to particular slave or to read from the slave. It was

achieved by different mode in which Master will be working like memory read

memory write and memory I/O modes. The Woking of Master in different modes

were coded in Verilog and the simulation results were verified

#2:

AMBA AHB-APB Bridge Basic Design

Tools: Xilinx,Modelsim

Language: Verilog

Description: The Advanced Microcontroller Bus Architecture (AMBA) specification defines an

on chip communications standard for designing high-performance embedded

Microcontrollers, AMBA AHB-APB Bridge Basic Design and Verification with

only one master and one slave. Architected the design and described the

functionality using Verilog HDL.

#3:

Implementation of Network on Chip in FPGA and Their Analyses

Tools: Xilinx,Modelsim

Language: Verilog

Description: Design and Development of routing architecture with five different channels for

communicating with Neighboring routers, Network on Chip routers provides

essential routing functionality for effective global on-chip communication with low

complexity and relatively high performance.

#4:

Software/Hardware Parallel Long-Period Random Number Generation Framework

Tools: Xilinx,Modelsim

Language: Verilog

Description: It is capable of Dividing WELL Stream into an Arbitrary number of independent

parallel substreams,Our Design Acheives a throughput of one sample per cycle and

runs fast as

423 MHZ on a Xilinx XC5VFX130T Field Programmable Gate Array Device.

ACADEMIA

B.E (Electronics & Communications) from Sri Muthukumaran Institute Of Technology in 2013 with 6.4

CGPA

XII from Govt Boys Higher Secondary School in 2009 with 80.5%

X from Govt Higher Secondary School in 2007 with 86.2%

PERSONAL VITAE

Attended 1 Week In-plant training programme at Vee eee Technologies in Chennai.

Visited Radio Astronomy Center in Ooty, TamilNadu.

Attended 1 day MATLAB workshop conducted by Pantech Solutions, Chennai.

Date of Birth : 4th May, 1992

Languages Known : English, Telugu, and Tamil

No: 34, Leelavathi Nagar,

Address :

Chikkarayapuram,

Near Mangadu,

Chennai-600 069.

Reference : Available upon request

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