Project Power

MEGHA RADHAKRISHNAN

Ragam House, Keraladeshwarapuram Malappuram -676307

Mobile: 887******* / 904-***-****. E-mail: *****.*********@*****.***

Dedicated, personable entry level professional seeking for a space to excel knowledge and build

career profile while enjoying dedicative effort towards work assignments as an active resource for a

team.

As a qualified entry level professional, I can offer the following value:

Good knowledge in electronics as well as electrical domains, have industry experience in

transformers and cloud computing technique.

Special interest in Low power devices, digital Electronics and CMOS Digital Integrated

Circuits.

Adaptive to new environment and quick learner.

Confident and team player.

.

EDUCATION

M.Tech VLSI Design 2012 – 2014

Amrita Viswa vidyapeetham, Coimbatore, India

B.Tech Electrical and Electronics Engineering 2008 - 2012

SCMS School of Engineering and Technology, Kochi, India

Higher Secondary 2006- 2007

Madhavanantha vilasam Higher Secondary School, Malappuram, India.

Matriculation 2004- 2005

Fathima Matha Higher Secondary School, Malappuram, India.

TECHNICAL SKILLS

Electronic Design: Competent user of HSPICE and Cadence PSPICE.

Worked on: Synopsys Design Compiler, IC Compiler, Star-RCXT TM,

Primetime, Xilinx, I Verilog, MATLAB and MAGIC.

Computer languages: Proficient in C

Platforms: Linux and Windows. Good knowledge of Microsoft Office Suite.

Assembly language: 8085, 8086 microprocessors and 8051, PIC microcontrollers.

ACADEMIC PROJECT PROFILE

M.Tech Main Project January 2014 - August 2014

FOLDING TECHNIQUE TO REDUCE POWER IN CMOS FLASH ANALOG TO DIGITAL

CONVERTER

• Flash ADC architectures based on Folding technique is implemented, which is less in area,

consume less power and provide fast response. By using folding technique number of

comparators gets reduced to half the number. . Reduction in comparators reduced power

consumption and total area used. Comparators are designed with build in threshold to reduce

more power.

• The project helped me in detail study of various Low power techniques for Flash ADC

architecture and their pros and cons. Moreover it helped me in improving my skills on IC

Design and also gave exposure to various design tools like Synopsys HSPICE, CADENCE

PSPICE etc.

M.Tech Phase I Project October 2013 - December 2013

POWER REDUCTION IN CMOS FLASH ANALOG TO DIGITAL CONVERTER BY

REDUCING COMPARATORS.

• Designed a Low Power Flash ADC using Multiplexers. Conventional resistive ladder is

eliminated for power reduction and multiplexers were used to produce reference voltage. For

n bit ADC this method required only n comparators where as conventional architecture

requires 2n -1.

• The project helped me in detail study of various ADC architectures and their pros and cons.

Implementation of Flash ADC is done in Synopsys HPICE using 90nm technology.

B.Tech Main Project November 2011 – June2012

ENOB MEASUREMENT IN DATA ACQUISITION UNIT USED IN SATELLITE LAUNCH

VECHICLE.

• Measured Effective Number of Bits in Data acquisition unit used in satellite launch vehicle.

ENOB is measured for estimating quality of signal. All real signals contain certain amount of

noise. ENOB specifies the number of bits in the digitized signal above the noise floor.

Developed at calibration and maintenance facility of Avionics Entity of ISRO .

• The project helped me in improving my skills on C programming and also gave exposure to

Life at Vikram Sarabhai Space Centre.

INTERNSHIPS AND WORKSHOPS

• In plant training on transformers at Kerala Electrical and Allied Engineering Co.Ltd

(KEL), Mamala, Cochin.

• International workshop on cloud computing organized by Microsoft and Indian Institute

of Hardware Technology at IIHT cloud campus, Info park,Kochi

• Research and project areas in VLSI Design: A one day workshop on Research and project

areas in VLSI, under the guidance of IETE

ACHIEVEMENTS

• Secured GATE scholarship from MHRD, Govt. of India. 2012 - 2014

• Secured several prizes in dance and story writing in state youth festivals. 2005 - 2008

• Selected as school leader and house captain and organized various 2005 - 2006

technical and cultural events.

PUBLICATIONS

Published a paper titled “IMPLEMENTATION OF LOW POWER FLASH ADC BY

REDUCING COMPARATORS” in IEEE International Conference on Communication and

signal processing, held in Chennai on April 3rd – 5th 2014.

Contact this candidate