Low power design,Digital Design,verification,SV,UVM,Asic Synthesis, C
Resume:
**************@*****.***
B Shravan Kumar
Resume
Objective
To secure a position in the organization that offers challenge and opportunity for my career development and at
the same time serve the organization to the best of my capabilities. I am looking forward to contribute to the research,
design, and development of VLSI systems by gaining new skills while utilizing my current area of expertise.
Professional Experience
Currently working as Digital Design Engineer with Redpine Signals India pvt Ltd. from 17th July 2013.
Computer Skills and Tools
Programming Languages: C, C++, Assembly.
Scripting Languages: Perl, TCL
Hardware Descriptive Language: Verilog.
Verification Languages and Methodologies: System Verilog, UVM.
Tools: Synopsis VCS, Synopsis Design Compiler, Synopsis Synplify Pro, Xilinx ISE, Mentor Graphics ModelSim.
Protocols: AMBA AHB, APB.
Work Experience
Working experience with UVM, System Verilog, RTL design and Integrating modules, ASIC Synthesis,
Formality and SpyGlass, Lint/CDC, RTL and Net list and Low Power Simulations
AHB2AHB Bridge Module level Verification
AHB2AHB Bridge is Host interface between Host and SoC ICM. It has one master and one slave on Host side and one
master, one slave and one extra DMA access path on SoC side. Apart from just transferring the data from Host to SoC and
SoC to Host, It has control and status registers which controls interrupt mechanism for SoC TA processor. For verifying
the A2A Bridge, modified Synopsis AHB UVM VIP’s example and created environment for verifying A2A Br idge. Used
Assertion IPs for verifying complete AHB 2.0 Protocol. Added test cases for verifying full functionality of A2A Bridge.
Participated in design, verification and synthesis for WLAN 1X1 11n IP
This Project is the complete design of WLAN 11n IP with Host Interface as AHB.
Roles: 1. Integrated AHB2AHB Bridge on ICM and various modules at SoC level in WLAN 1x1 11n IP.
2. Designed Digital IQ Interface with DDR (Double Data Rate) logic for transmitting and Receiving Digital IQ
Samples.
3. Created the Test environment by taking CHIP level UVM TB and added and modified some test sequences
specific to this IP. Got experience with complete Chip level functionality.
4. Did the ASIC Synthesis (Ultra) for the 11n IP and added UPF Flow for specifying power intent in power
optimization.
5. Wrote clock gating, pll, isolation controller modules for clock tree and power domain Changes.
6. Got Good Exposure on to IP Design, VLSI Flow, Backend Requirements.
Participated in Design of MCU based CHIP
This chip is Completely ARM Cortex-M4 based MCU CHIP.
Roles: This is dividing Zigbee, Bluetooth MAC into two power domains for power optimization. Integrated new
Peripherals like GSPI, QSPI on ICM and AHB2APB IP’s Bridges. Peripherals and Chip level interface signals are muxed
onto GPIO’s. Divided SoC, Processor, and Peripherals into different power domains. Done respective Clock tree and
Reset Architecture changes. Did DC Synthesis (ultra) up to SoC subsystem level and added Spyglass and Formality
Environments.
Done FPGA synthesis for Vertex-5 and done respective RTL changes in RTL. Created Testcases, done firmare changes
for Low Power Simulations, tested basic functionalities and dependencies of various power domains.
Scholastic Record
M.Tech -- Very Large Scale Integration (VLSI) - 2013
Inst it ution Indian Inst itute of Techno log y, Guwahati
Cumulative Performance Index (CPI) 8.00
B.E -- Electronics and Communication Engineering (ECE) - 2010
Inst it ution Vasavi College of Engineering, Affiliated to Osmania University, Hyderabad
Percentage 68.64%
Class XII – Board of Intermediate Education, A.P - 2006
College Name Vignan Junior College, Vadlamudi, Guntoor
Percentage obtained 94.90%
Class X -- State Board of Secondary Education, A.P - 2004
School Name Siddhartha High School, Karimnagar
Percentage obtained 89.00%
Research Experience
M.Tech Project, “VLSI implementation of Sign-LMS based Adaptive Filter using SPT algorithm”
(Advisor: Dr. S. R. Ahamed, IIT Guwahati)
This Project presents VLSI Implementation of Variances of LMS algorithm, called Sign-LMS for realization of Adaptive
Filter Coefficients using Sum of Power of Two (SPT) algorithm to simplify the Hardware complexity. By using this
algorithm, multipliers are removed in the Weight updating block.
Tools: Xilinx 10.1
B.E Project, “Image Blur Reduction in Cellphone Cameras using ATC”
(Advisor: Asst. Prof. M.Shyam Sundar)
This Project presents an image blur reduction for cellphone cameras having a low computational complexity and without
making any assumption about the background blur. This algorithm utilizes one low-exposure image in addition to a
blurred image to perform a blur reduction operation via ATC.
Tools: MATLAB
Achievements
Got 1628th (< 1%) Rank in EAMCET which is entrance test for Engineering.
Got 366th Rank with Gate Percentile of 99.80 in GATE 2011.
Participated in various talent tests, quiz Competitions and won Prizes at school level.
Extra Curriculars
Member of EEE Volley Ball and Cricket Teams for Advaya’12 in IITG.
Member of ECE cricket team in Vasavi college of Engineering
Playing Chess, Volleyball, Table Tennis and Cricket.
Personal Details
Full name Shravan Kumar B Mailing Address c/o Subramanyam
H.no- EWS 501,
21st Dec 1988
Date of Birth Near Temple Bus stop,
KPHB colony, Hyderabad, A.P
Gender Male
Permanent Address s/o Bhoomaiah Burra
Nationalit y Indian SD-53, Naspur colony,
Mancherial,
Email **************@*****.***
Adhilabad- 504302.
Andhra Pradesh, India.
Contact number +91-970*******
DECLARATION
I hereby declare that all the above information is correct to the best of my knowledge and belief.
Date: 01/11/2014
Place: Hyderabad
(Shravan Kumar Burra)
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