Senior Ecad Design engineer
Resume:
SANDRO M. LANOT
San Juan Taytay Rizal
+639********* Philippines 1920 ***********@*****.***
+639*********(Home)
SUMMARY
Offers 14 years of solid experience in PCB Layout Design(start to finish), along with 5 years Team Management and Leadership . Have strong work ethics, a dedication to team environment, an eagerness to strive for perfection, and an emphasis on customer satisfaction.
SKILLS
Tools: Cadence Allegro, Mentor PADS, Mentor Boardstation, CAM350
Capabilities: Start to finish PCB layout, fabrication and assembly drawing, stack up creation and approval, gerber file creation and checking
Technologies: HDI, SMT/PTH/Mixed, MLB, high speed design
Form Factors: Motherboards, Servers, and all daughter cards that completes the whole system
Layer Count: Up to 16 Layers
Complexity: DDR3/4, PCIE, QPI, SAS/SATA, USB, 10 GB Ethernet
Standards: IPC, DFM, DFT
Others: Microsoft Office Tools, Lotus Notes, Agile
EXPERIENCE
Foxconn Technology Group
No. 2 2nd Donghuan Road, 10th Yousong Industrial District
Longhua, Baoan Shenzhen City, Guandong Province, China Code: 518109
Senior PCB Layout Engineer - Team Leader (March 7,2010 - April 16, 2014)
Start to finish PCB layout design(board outline, constraints management, component placement, routing, length matching, power plane, DRC, testpoints, silkscreen, gerber release to PCB vendor and vendor EQ’s.
Placed/routed server and storage solution topologies such as CPU VRD, DIMM VRD, CPU misc, PCH, GLP and IO blocks.
Set up physical, spacing and electrical constraints of DDR3/DDR4, QPI, PCIE, SAS/SATA, USB, and other major buses of a server and storage platform.
Quality control of the team’s designs to ensure they adhere to DFM/DFT standards. Reviewed and approved all gerbers before uploading to Agile.
Worked closely with the project team for the schedule and features tradeoffs to ensure design release on time.
Closed the loop with PCB vendors whenever engineering questions and deviations arise within a particular design.
Interfaced with PM's, EE, ME, SI, Safety, Thermal, DFM and DFT team during design development .
Updated the PCB layout process flow that includes process documentations and guidelines to catch up with the latest industry technologies and standards.
Provided continues technical training to freshman and junior employees .
Grew PCA drawing group that is responsible for drafting PCA drawings for L6-MFG usage.
Promotions Achieved:
Group Leader(August 2011) - Leads 5 - 7 engineers
Team Leader(October 2012) - Leads whole layout team of 35 - 40 engineers
Bitmicro Networks International Inc.
#19F Netsquare Center 28th Street Corner 3rd Avenue, Crescent Park
West Bonifacio Global City, Taguig 1634 MM. Philippines.
Senior PCB Layout Engineer (September 2004 - August 2009)
Start to finish PCB layout design(board outline,, component placement, routing, length matching, power plane, drc,, silkscreen, gerber release to fabrication and assembly)
Reduced and recommended mounting strategies and layer count for PCB cost reduction.
Trained freshman and junior engineers.
Performed PCB incoming Inspection following IPC600-G.
Resolved technical issues within the whole PCB layout team.
Provided know-how and latest techniques in using the tool.
Checked the PCB data and gerber files to ensure quality and correctness of board before submitting them to PCB vendors.
Promotions Achieved: Project Leader (May 2005), Senior Project Leader ( January 2006), Senior Technical Leader (January 2007), and Head Technical Leader (April 2008)
Wistron InfoComm Philippines Corporation
Olongapo City, Philippines
PCB Layout Engineer (May 1999 to September 2004)
Worked on the PCB layout of motherboards for notebooks, desktop, and servers; consumer boards and expansion cards.
Provided manufacturing data for fabrication.
Trained colleagues on using Cadence Allegro and Mentor BoardStation.
Authored several skill programs to automate layout process.
Was sent to Wistron InfoComm Headquarters in Taiwan to support and manage all the projects that needs to be catered in the Philippines every year for the duration of 1 month to 6 months each time.
Promotions Achieved: Junior Engineer (July 2001), Engineer ( January 2003), Senior Engineer (June 2004),
TRAINING
Under Bitmicro Networks Inc. ( inhouse management seminars)
November 5-7 2008 Bringing Out The Leader In You
July 9-11, 2008, Effective Project Management
June 3-6 2008 ISO9001-Seminar Workshop
October 10-13, 2006, Emphasizing On People In People Management
Under Wistron Infocomm (Taiwan Acer Headquarters for training and support)
September 5 – October 5, 2003, Cadence Allegro15.2
June 20 - August 17, 2001- Mentor Graphics Boardstation
June 28 - December 20, 2000 –Mentor Graphics Boardstation
EDUCATION
B.S. in Computer Engineering
Adamson University, San Marcelino, Manila, Philippines (1993-1998)
Dean’s lister, PESFA Scholar, Class President
High School Valedictorian, Pola Catholic High School, Pola Or. Mindoro, Philippines (1989-1993)
Student Body Organization President, Math and Science Club President
Elementary School Valedictorian, Pola Central School, Pola Or. Mindoro, Philippines (1983-1989)
Student Body Organization President
Contact this candidate