verilog,c language,rtl design,testbech verification,linux,xilinx.

R ajeev verma

Email: - **************@*****.***

Phone No: +91-857*******

O bjective:

To work with a highly dignified organization offering challenges and growth with

opportunities to enrich my knowledge and skills while contributing my best to the

organization I work for.

Technical Skills:

C

Programming Languages

Verilog,Matlab,Labview

Modelling Languages

Verilog

Verification Languages

Windows, Linux

Operating systems

Xilinx Synthesis Technology (XST)

Synthesis tools

Xilinx ISE simulator,, iverilog

Simulation tools

P rofessional Experience:

• Currently doing I n te rnship i n VLSI design technology at JBTech India

(from Sep. 2014 to t ill date)

• Academic T raining: J BTech India, Greater Noida(Uttar Pradesh) (4 weeks

part of curriculum):

Study of Verilog, working on L inux and team based environment, basics of

FPGA.

P rojects du r ing t raining -:

Project 1: F I FO Design

Description:

A F irst in First out (FIFO) is a queue of data, where the data which is writ ten fi rst, is read

out first. FIFO has read and wri te pointers for read and wri te operations into the queue.

Read and wri te operations are synchronized with the clock. Depending upon the data stored

i n the FIFO, Empty and Full f lags as well as fifo_almost_full and fifo_almost_empty f lags

a re set. During read operation, data is read from fifo_ram memory. During wri te operation,

data is wri t ten into fifo_ram memory

L anguage Used: Verilog

Tools Used: X ilinx ISE project navigator

Project 2: RAM Design

Description:

Random-access memory is a form of computer data storage. A random-access memory device

allows data items to be read and written in roughly the same amount of time regardless of the

order in which data items are accessed.

Language Used: Verilog

Tools Used: X ilinx ISE project navigator

Project 3: Data handler and controller

Description:

Data Handler is loaded in situations when other handlers were not used, which is most

commonly for regular web page requests. Data Handler takes all the input from GET, POST,

FILES; SESSION and COOKIE variables, loads Wave Framework API and sends all the input to

the API.

Language Used: Verilog

Tools Used: X ilinx ISE project navigator

Project4 : Clock Gated Low Power Sequential Circuit Design

D escription : In this work, our focus is on study and analysis of various clock gating technique

and design and analysis of clock gating based low power sequential circuit at RTL level. Clock

gating is implemented on smaller circuit called D flip-flop and on larger circuit called 16-bit

register.

Responsibilities:

Involved in coding as well as hardware interfacing of the project.

Language Used: Verilog

Tools Used: X ilinx ISE project navigator

Project5: Carry Select Adder with Low Power and Area Efficiency

Description : In performing fast arithmetic functions, Carry select adder (CSLA) is one of used in

many data processing processors to perform fast arithmetic functions. CSLA (SQRT CSLA) architecture

have been developed and compared with the regular SQRT CSLA architecture. The proposed design has

reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the

delay. This work evaluates the performance of the proposed designs in terms of delay, area, power.

Language Used: Verilog

Tools Used: X ilinx ISE project navigator

Achievements:

• Awarded for 100% attendance at school level.

• Cricket captain in school.

Extra Cur r icular Activities:

• Member of the college cricket team.

• Member of galaxy (branch association).

• Attended seminar on biomedical instrumentation and measurement

S trengths:

• Hard working, dedicated and sincere towards work

• Team player, optimistic and futu ristic.

Hobbies:

• Playing chess and cricket.

Educational Qualification:

Course Subjects I nstitute University Year Percentage

Electronics & Anand UPTU, 2011-15 64.81%

B.Tech. Communicatio engineering L ucknow (till 6th

n Engineering college,agra semester)

G reen field CBSE Board 2011 52.2%

S.S.C (12 )th

PCM academy

l akhimpur-

kheri U.P.

Paul CBSE Board 2009 69.4%

H.S.C (10th ) ALL i nternational

school,lakhimp

ur- kheri U.P.

Personal Details:

Date of Bir th : November 29th, 1993

Mari tal Status : U nmar ried

Permanent Address : Vill and post-Mahewaganj, district-lakhimpur kheri 262701

U.P

P resent Address : House no.22,bajarang nagar, sikandra agra 282007 U.P.

Contact No. : +91-857*******

Contact this candidate