Project Engineer

A nusha G

Email: acgphu@r.postjobfree.com

Phone No: 91-949*******

Results Focused I T professional offering a t rained engineer t o devote my skills and

k nowledge for the fulfillment of the company’s goal and to lea rn new technologies &

t echniques in physical design to enhance my skills and abilities.

P rofessional Synopsis:

T rained in Physical Design at ISS Madhapur Hyderabad.

Familiar with the concepts of ASIC Physical Design (P & R, RTL to GDSII) Flow, Sign Off

activities.

Effective interpersonal skills with abilities to meet deadlines & work under pressure.

Solid Understanding of basic Electronics.

Expertise in block level place and route on TSMC 130nm and 90nm technologies.

Good Knowledge in Timing Analysis, Crosstalk Analysis, IR Drop Analysis & EM.

H ands On Tools:

ASIC P & R (RTL TO GDSI I) Skills in Cadence tool chain:

Floor Planning, Place & Route, CTS and Timing Closure - Cadence SOC Encounter.

Static Timing Analysis and Crosstalk Analysis -Encounter Timing System.

Logic Synthesis -RTL Compiler.

Physical Verification- Assura.

Custom layout -Vi r tuoso.

Analog Simulation- Spectre.

Good knowledge in VHDL & Verilog.

Xilinx ISE for Simulation.

Have basic knowledge in SHELL, TCL Script & L inux Commands.

P roject Details:

Project#1 : PC I DATA

Project Type : Top Level

Objective : Timing D r iven Layout

Tool : SOC Encounter,ETS

Technology : U MC 0.18micron, 5 Metal Layers

Macros/STD Cells : 12/24461

Gate Count/Area :1,28,920/1572423.4 um^2

Clocks : 8 C locks, Max 150 M Hz

Role : D ie size, PG planning, Performing sanity check, Design import, Floor Plan, Power

P lan, Placement, Tr ial Route, Power Analysis, RC Extract, Timing analysis, IPO, CTS, Detailed

routing.

Project#2 : (Block Level)

Project Type : Block Level

Objective : Timing D r iven Layout

Tool : SOC Encounter,ETS

Technology : T SMC 0.18micron, 5 Metal Layers

Macros/STD Cells : 12/27061

Gate Count/Area :3,03,884/1547443.2 um^2

Clocks : 17 Clocks, Max 200 M Hz

Role : Performing sanity check, Design import, Floor Plan, Power Plan, Placement,

T rial Route, Power Analysis, RC Extract, Timing analysis, IPO, CTS, Detailed routing

BRX_TOP ( BLOCK LEVEL):

O bjective : T iming D r iven Layout

Tools : SOC Encounter, ETS.

Gate count : 11000

No. of Clocks :3

F requency : 150M Hz

T echnology/Layers : TSMC 0.18 micron/5 Metal Layer

Role : Performing sanity check, Design import, Floor Plan, Power Plan, Placement, T r ial

R oute,

Power Analysis, RC Extract, Timing analysis, I PO, CTS Adding Filler cells.

LOG IC SYNT HESIS:

Tools : RTL Compiler

No of clocks :2

F requency : 200MHz

Role : Prepared Constraint file, TCL file, Performed Wire load and Zero Wire load

M odel Timing

C hecks.

LAYOUT:

Standard Cells Layout Designing:

Tools : Vi rtuoso Layout Editor, Assura Verification.

Design : L ayout of a CMOS gates.

Role : D rawing the stick diagram from spice net list, drawing layout and verifying

D RC and LVS.

Academic Qualifications:

Pursuing M aster of Technology (VLSI DESIGN ) secured with 78.00% f rom J NTU KAK INADA

d uring 2013-2015.

Distinction in B achelor of Technology (ECE) secured with 85.74% f rom J NTU HYD d uring

2008-2012.

Distinction in I ntermediate secured with 93.90% f rom Board of Intermediate (2006-2008).

Distinction in S.S.C secured with 88.00% f rom Board of Secondary Education during 2005-2006.

Personal P rofile:

Date of Birth : 12 April 1991

Nationality : I ndian

Passport Status : Valid

Ma r ital Status : Single

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