Project Data
Resume:
Raju Ratan Chaubey
Email: - ***********@*****.***
Phone No: +91-854*******
Objective:
To work with a highly dignified organization offering challenges and growth with opportunities to enrich
my knowledge and skills while contributing my best to the organization I work for.
Technical Skills:
Programming Languages C
Modelling Languages Verilog,Matlab,Labview
Verification Languages Verilog
Operating systems Windows, Linux
Synthesis tools Xilinx Synthesis Technology (XST)
Simulation tools Xilinx ISE simulator, iverilog
Professional Experience:
• Currently doing Internship in VLSI design technology at JBTech India (from Sep. 2014
to till date)
• Academic Training: JBTech India, Greater Noida(Uttar Pradesh) (4 weeks part of
curriculum):
Study of Verilog, working on Linux and team based environment, basics of FPGA.
Projects during training -:
Project 1: FIFO Design
Description:
A First in First out (FIFO) is a queue of data, where the data which is written first, is read out first. FIFO
has read and write pointers for read and write operations into the queue. Read and write operations are
synchronized with the clock. Depending upon the data stored in the FIFO, Empty and Full flags as well as
fifo_almost_full and fifo_almost_empty flags are set. During read operation, data is read from fifo_ram
memory. During write operation, data is written into fifo_ram memory
Language Used: Verilog
Tools Used: Xilinx ISE project navigator
Project 2: RAM Design
Description:
Random-access memory is a form of computer data storage. A random-access memory device
allows data items to be read and written in roughly the same amount of time regardless of the
order in which data items are accessed.
Language Used: Verilog
Tools Used: Xilinx ISE project navigator
Project 3: Data handler and controller
Description:
Data Handler is loaded in situations when other handlers were not used, which is most
commonly for regular web page requests. Data Handler takes all the input from GET, POST,
FILES; SESSION and COOKIE variables, loads Wave Framework API and sends all the input to
the API.
Language Used: Verilog
Tools Used: Xilinx ISE project navigator
Project4 : Clock Gated Low Power Sequential Circuit Design
Description: In this work, our focus is on study and analysis of various clock gating technique
and design and analysis of clock gating based low power sequential circuit at RTL level. Clock
gating is implemented on smaller circuit called D flip-flop and on larger circuit called 16-bit
register.
Responsibilities:
Involved in coding as well as hardware interfacing of the project.
Language Used: Verilog
Tools Used: Xilinx ISE project navigator
Project5: Carry Select Adder with Low Power and Area Efficiency
Description: In performing fast arithmetic functions, Carry select adder (CSLA) is one of used in many
data processing processors to perform fast arithmetic functions. CSLA (SQRT CSLA) architecture have
been developed and compared with the regular SQRT CSLA architecture. The proposed design has
reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the
delay. This work evaluates the performance of the proposed designs in terms of delay, area, power.
Language Used: Verilog
Tools Used: Xilinx ISE project navigator
Achievements:
• School captain.
Extra Curricular Activities:
• participated in poster competition.
• Member of galaxy (branch association).
• Attended seminar on biomedical instrumentation and measurement .
Strengths:
• Smart worker.
• Hard working, dedicated and sincere towards work
• Team player, optimistic and futuristic.
Hobbies:
• Playing chess .
• Thinking new ideas.
Educational Qualification:
Course Subjects Institute University Year Percentage
Electronics & Anand UPTU, 2011-15 61.81%
(till 6th
B.Tech. Communication engineering Lucknow
Engineering college,agra semester)
A.P.P inter UP Board 2011 60%
th
S.S.C (12 ) PCM college palahi
patti, varanasi,U.P.
S.S.N inter UP Board 2007 63.5%
H.S.C (10th ) ALL college ayar,
Varanasi, U.P.
Personal Details:
Augst 22nd, 1992
Date of Birth :
Marital Status : Unmarried
Permanent Address : Vill and post-Palahi Patti, district-varanasi,221208 U.P
Present Address : House no.89,bajarang nagar, sikandra agra 282007 U.P.
Contact No. : +91-854*******
Contact this candidate