VLSI and Embedded System Fresher

PRADEEP S R

Mobile: +91-997*******

E-mail: ***********@*****.***

“Developing the career through individual & organizational development and to deliver

my duties very sincerely and regularly in the interest of organization”

Professional Credentials

M.Tech (VLSI Design & Embedded Systems) at Department of PG Studies, VTU, Gulbarga

with an aggregate of 73%.

9 months industrial experience and 1.4 years teaching experience.

2 Research Papers presented in National Level Conference and 6 Research papers published

in International Journals respectively.

Able to communicate effectively.

Work Experience

SIRIUS CONNECT PVT. LTD, BANGALORE Oct ’09 to July 2010

Web Developer

Responsibilities handled:-

Designing Websites in Real Estate Business for US clients.

Domain registration, SEO Analysis.

Worked as a group leader to handle a team of 5 members.

SHRIDEVI POLYTECHNIC, TUMKUR Feb ’11 – June ‘12

Lecturer

Responsibilities handled:-

Handling Subjects: DE, CP, BCS Lab, AEC, MC, and IA.

Additional Duties : Academic In charge, Timetable In charge, I/C HOD.

Educational Credentials

COURSE INSTITUTION UNIVERSITY PERCENTAGE YEAR

1st Sem 68.8

M.Tech (VLSI

Dept. of PG 2nd Sem 68.5

Design &

Studies, VTU, VTU, Belgaum 73 2014

Embedded 3rd Sem 74.4

Gulbarga

Systems) 4th Sem 92.3

B.E (ECE) Aggregate 56 2009

HMSIT, Tumkur VTU, Belgaum

PUC(10+2) from Govt. Science College, Madhugiri, Department of Pre-University Education in

2004.

SSLC (10) from Sri Siddartha Residential High School, Madhugiri, Karnataka Secondary

Education Board in 2002.

Project Details

Project

VLSI (back end design) based project called “Design & Implementation of AXI Bus

architecture on FPGA & its verification environment in System Verilog using UVM

Technique” by the completion of my Master degree.

Embedded System based project called “Voice Based Elevator Moment using RTO’s” by the

completion of my bachelor academic.

Mini - Projects

VLSI based project called “Wallace Tree Multiplier”.

VLSI based project called “A New Reversible Design of BCD Full Adder”.

Presentation & Publications

[[[

The paper entitled “Realization of AXI Protocol on FPGA with 256 data transfers per

burst” presented in AICTE Sponsored National Conference on Recent Advances in

Communication Networks – NCRACN’14.

The paper entitled “Design & Verification environment of AMBA AXI Protocol for SOC

Integration” presented in NCRIET’14 and it is published in International Journal of Research in

Engineering & Technology, Vol. 3, Special Issue 3, pp 338-343.

The Paper entitled “High Speed Pipelined Data Encryption Standard with Error Detection

and Correction” published in IJTRE (International journal for Technological Research in

Engineering), Volume 1, Issue 1, and September 2013,pp 80-86.

The paper entitled “LSSR: LECTOR Stacked State Retention technique A novel Leakage

reduction and State retention Technique in low power VLSI design” published in IJERT

(International Journal of Engineering Research & Technology), Vol. 2 Issue 10, October – 2013.

The paper entitled “Low Power and High Speed BCD Adder using Reversible Gates”

published in “International Journal of Electronics, Communication & Soft Computing Science

and Engineering”, ISSN: 2277-9477, Volume 2, Issue 9, pp 20-25.

The Paper entitled “Automation of Railway Yard Container Handling Robotic Hoist”

published in IJERT (International journal of Engineering Research & Technology), ISSN: 2278-

0181, Volume 3, Issue 4, and April - 2014, pp 2061-2065.

The Paper entitled “Efficiency of Entropy Coding as well as Dictionary based Technique

for Lossless Data Compression” Manuscript ID:- IJRDT1000039 in International Journal for

Research & Development in Technology for Vol. 1,Issue.1.(May 2014)

Technical Skills

Computer Information : Basic Computer knowledge with MS Office, Excel, PowerPoint etc.

Operating System : Windows XP, 2003, 07, 08 & Linux.

Software Skills : C, Microcontroller, PCB, Verilog, System Verilog.

Interesting Areas : VLSI Platform, Embedded Systems.

AWARDS

Getting Star Performer Award for February 2010, from Sirius Connect Pvt. Ltd.

Personal Profile

: 09th June 1986

Date of Birth

Nationality : Indian

Marital Status : Single

Caste : SC (Adi dravida)

Languages Known : English, Kannada, Telugu and Hindi

Postal Address : Venkateshwara Nilaya, Urdu School Main road, Upparahalli, TUMKUR –

572102.

Strengths : Friendly Nature, Punctuality, Hard Working.

Sports & others : Participated District Level competition in Volleyball & Badmitton and

Participated in Cultural Activities in District level Competition.

Date: Yours sincerely,

Place:

(PRADEEP.S .R)

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