Peijian Yuan
(US citizen)
Phone: 202-***-**** E-mail: **********@*****.***
OBJECTIVE
Seeking engineering position on Hardware/Embedded system/FPGA design and firmware coding.
SUMMARY
* ***rs of experience in leading design of appliance product include functional definition, architecture design,
component selection, schematic/layout, debugging firmware and product testing (ESD, EMI, UL, etc.).
Over 10 years of experience in the board level design, assembly, debugging, FPGA programing and firmware coding
of a variety of boards, embedded control systems and DSP algorithms.
4 years of experience in the design and verification of integrated circuits for communication networks.
Over 10 years of R&D experiences in optics-electronics-mechanical field with various sensors, including optical grating,
accelerometer, audio MEMS, and stress transducers.
SKILLS
Electrical Architecture/Circuit Design/PCB Layout: Cadence, OrCAD, and Altium/Protel 99.
Test Equipment: Oscilloscope, Logic Analyzer, Spectrum Analyzer, Signal Generator, ESD tester, etc.
Firmware Design: TI DSP OMAP-L138, Renesas RX210, ARM based, Intel 8051 based assemble, C/C++ with
IDE of CCS, HEW, IAR, Keil.
FPGA/ASIC Design: VHDL, Verilog, Perl and UNIX shell scripts. (G-bit Ethernet chip and Xilinx FPGA)
Others: Ethernet, SONET, ATM, MPEG, PCI Bus, USB, DSP, RFID and UWB, UART, I2C and SPI interfaces.
Ability to maintenance and repair the electrical/sensor devices and mechanical machineries.
WORK EXPERIENCE
Lead Design Engineer General Electronic, Louisville, 2011 - Present
Renesas microcontroller and Atmel touch chip based product - cooktop user interface:
Design cooktop user interface board (controller and touch panel) include function definition, schematic design,
PCB layout, firmware and product testing (ESD, EMI immunity, EMI emission, line interrupt, aging and UL).
Testing the WiFi module and Zigbee module connected to internet on appliances (range oven, wall oven, and
dishwasher), focus on RSSI and error rate.
Patent pending : Cooktop Appliances with Intelligent Response to Cooktop Audio (274770-1/GECA-606)
Senior Design Engineer ST Microelectronics, Phoenix, 2000 - 2011
STM32 (ARM core) microcontroller based projects:
Implemented Control function for STA2500D Bluetooth chip by STM32 microcontroller in C, included initialization,
pairing and file transmission. Schematic and board layout (0.25BGA, 2.4GHz) with strain gauge, instrument amplifier,
STM32, Bluetooth chip STA2500D, antenna, etc.
Implemented applications for STM32-Based “Digital” Power Conversion. DC-AC inverters with Watch-dog fault
detection, Full-wave rectified sine wave, high-voltage switched full bridge and regulators with buck, Boost, Buck-Boost
by PWM technology. Schematic, board layout and driver programming in C.
STw5098 codec application include configuration, modes setting and data transceiver with I2C, I2S, SPI and PCM
interfaces based on STM32 microcontroller. Level shift board layout and components assembly.
Firmware coding for STM32 microcontroller including clock generation, data accumulation and FIR filter (DSP) in digital
phone (MEMS) application.
SpearHead (ARM core with programmable area) processor based projects:
Created RTL programs for a Xilinx XC4VLX60 FPGA in VHDL for clock generation, windowed / no windowed scan,
data accumulation and FIR filter in digital phone (MEMS) application. Application collected data from an FPGA, stored
data on memory and sent it to host using SpearHead in C.
Created RTL programs for a Xilinx FPGA using VHDL for HDD adapter with PIO4, DMA and UDMA modes, NOR /
NAND flash, security chip and CMOS sensor VC5602 interfaces. Firmware coding to control data transceiver between
SpearHead, FPGA chip and host. Schematic, board layout and components assembly of daughter board.
Nomadik (ARM core multimedia processor) based projects:
Coded CPLD in Verilog for HDD adapter with PIO4 mode based on Nomadik FSMC interface. Schematic, board
layout and components assembly daughter board for 1.8” HDD and daughter board for ECL clock driver.
ASIC Verification projects:
Coded Verified G-bit Ethernet, EAGLESCAN VC5602 and VOIP System on Chip test cases in Verilog.
Wrote STPH68, STPHY8, Quad PHY and SMII modules test benches in Verilog.
Customer application projects:
Designed Human heart pulse test circuit with optical sensor, PCB layout and test program.
Board layout and components assembly of computer high current switch power supply, linear amplifier, high-pass, low-
pass filter.
System design, board layout, components assembly of digital wireless group phone with CC1020 transceiver and
SPCE061A sound controller.
Principal Engineer VIVE Synergies Inc. Toronto Canada 1998 - 2000
Voice Over IP (Internet Phone) Stand Alone Device
A marketing product using PowerPC 860T processor and TI TMS320VC5402 DSP based system with 10 Base-T
Ethernet interface, RS232 interface, ISDN multi-channel transceivers, PCM switch and 2-4 wire converter.
Responsible for functional specification, architecture, schematic, and layout design.
Senior Engineer Institute of Mechanic, Chinese Academy of Science, China 1986 - 1996
Research and development project for new technology application:
Multi-channel Micro-flow Meter for Bio lab based on some special functions as accuracy balance, channel
control, A/D converter, parallel interface and PC control.
Universal All Digital Programmable ULF Signal Generator, application in material strength and vibration testing.
Designed an Ultra-stable multi-channel DC amplifier which performed weak signal measurement using various
strains and sensors in oil platform, building foundation, medical and environment protection field.
Mechatronics design for caliper with grating, phase detector and display technology.
An industrial environment control unit for 1.5 meter diameter stone cut machine.
MIL-STD-1553B Multi-BUS interface with hardware implemented sync detect in aircraft distributed computer.
EDUCATION
MSEE Institute of Polytechnique, University of Montreal, Canada
Department of Electronic and Computer Engineering
B.Eng Beijing University of Aeronautics and Astronautics, China
Department of Computer Science and Engineering