Nishanth Panchakshari

**** * *** ******, #***, San Jose, CA-95112

acgp06@r.postjobfree.com Ph no: 714-***-****

OBJECTIVE Seeking opportunities in the field of VLSI with emphasis on ASIC design and/or

verification.

EDUCATION Master of Science, Electrical Engineering GPA: 3.43

San Jose State University, San Jose, CA

Concentration: Logic Design/Digital Systems

Bachelor of Engineering, Electronics and Communication GPA: 3.50

People’s Education Society Institute of Technology, Bangalore, India

TECHNICAL Hardware Description/Verification Languages: Verilog, System Verilog, VHDL.

SKILLS AND Programming Languages: C, Perl, Assembly(8051,8086), Java(Android), Python.

TOOLS Protocols: UART, I2C, AMBA AHB, AMBA APB, SPI.

Synthesis/Simulation Tools: Synopsys(VCS, Design Vision,Primetime), IVerilog,

Cadence-NCVerilog, Modelsim, VirSim, Altera Quartus, GTK Wave, Xilinx IDE.

Software Tools: GCC, Eclipse IDE, Microsoft (Word, Powerpoint).

Others: Object oriented programming, Windows, Linux, Unix, SVN and Doxygen.

EXPERIENCE Electrical Engineer - Automation Jun14 to Present

Shiva Systems, Santa Clara, CA

• Developed or Improved Perl scripts to parse the log file and modify test cases.

• Based on the new features, automated the complete flow using scripts and

documented the same.

Instructional Student Assistant(ISA) Aug 13 to Dec13

San Jose State University, San Jose, CA

• Lab Instructor and Evaluator for the courses - SOC Design and Verification

using System Verilog, Microprocessor based System design.

Android Development Intern Aug 12 to Dec12

Agreeyamobility, Mountain View, CA

• Developed customized UI and SQLite databases for android based applications.

• Utilized REST APIs of one drive to extract and authenticate information for

the android applications.

Project Trainee Mar10 to May10

Bharat Electronics, Bangalore, India

• Developed a robust embedded system to detect automobile hazards called “Emer-

gency Detection System as a part of final project.

• The system included location tracking services using GPS along with informa-

tion transmission through GSM to other display devices.

RELEVANT Advanced Logic Design and Synthesis, ASIC VLSI Design, Advanced Computer

COURSEWORK Architecture,SOC Design and Verification using System Verilog, Microprocessors

(8086), Microcontrollers (8051), CMOS VLSI Design, Analog and Mixed Mode VLSI,

Introduction to Programming in Python.

RELEVANT Parametric Floating Point Unit Implementation/Validation

PROJECTS • Designed to change the characteristics of FPU based on the input parameters.

AND • Implemented multiple algorithms to provide distinctive performance solutions.

PAPERS • Verified the design for single and double precision floating point numbers,

capable of handling exception conditions and different rounding modes.

Serial Peripheral Interface using Wishbone/Verification of MIPS processor

• Designed a serial peripheral interface using a wishbone interface in System

Verilog, which supports variable length data transfer in full duplex mode.

• Given the design specification for MIPS Processor,verified the DUT using Sys-

tem Verilog for maximum functional coverage with constrained random testing.

• Verification environment was made similar to UVM by creating classes for-

Monitor,Checker,Driver,Interface,and Sequencer; emphasizing code reusability.

• Used SVN for version control and documented the design using Doxygen

Embedded I2C Bus Controller with a Ring Bus Interface

• Designed a 32-bit low speed I2C controller as a part of Ring bus enabling end

to end communication in Verilog RTL.

• I2C configuration included a clock divider to accommodate for devices operating

at different frequencies, fifo status, transmit/receive count, interrupt control to

handle external interrupt and I2C state status.

• Design was rigorously tested using random tests and directed tests to ensure all

the requirements of the specifications were met accordingly.

• Simulated the deisgn in VCS, NC Verilog and IVerilog; Synthesized the design

in Design Vision with successful Gate level simulation in NC Verilog.

Design and Analysis of Area-delay and Power-delay trade offs in Addition circuits

• Implemented 16/32/48/64 bit carry lookahead and ripple carry adders for Static

timing analysis and Power analysis using Toshiba TC240 library.

• Optimized the design using timing constraints with trade off’s in timing, area

and power.Successful post synthesis verification for the net-list generated.

• Automated the flow using scripts to report area, timing and delay of the design.

Synchronous/Asynchronous FIFO Implementation and Verification

• Implemented Synchronous/Asynchronous circular FIFO with external memory

interface to handle burst data in Verilog HDL.

• Verified the design using test bench written in System Verilog

SUMMARY • Proficient in Logic Design concepts-implementing and optimizing state ma-

chines, analysis and synthesis of synchronous and asynchronous digital circuits.

• Hands on experience in designing digital circuits with Verilog HDL at behavioral

level and RTL level; develop test benches to verify the design by simulation.

• Experience with Static and Dynamic timing analysis with false paths and haz-

ards; implementing synthesizable circuits with trade off’s in timing, area and

power.Improve performance by pipelining and parallelism.

• Experience with verification using System verilog with good knowledge in con-

strained random stimulus and directed testing along with functional coverage.

• Good programming knowledge in C, Java (Android), OOP concepts and Perl.

• Excellent understanding of computer architecture concepts, Microprocessors(8086),

Microcontrollers(8051) and assembly language programming.

LINKEDIN: www.linkedin.com/in/nishanthpanchakshari

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