Actively looking for fulltime position in Digital Design, ASIC

Karthik Naishathrala Jayaraman

Plot No: **, Door No: 2/1762, Enfield Avenue, Madipakkam, Chennai-600091, India.

Mobile: +91-893*******. Email: ************@*****.***

Objective

To obtain a fulltime position in the field of Digital Design/ASIC Design/Physical Design/Architecture.

Summary of Qualifications

Expertise in Low Power VLSI Design, VLSI design, Physical Design, Computer Architecture and Design, VLSI

testing, Timing analysis, power analysis, NAND and DRAM Memory, EDA tools and scripting.

Education

Master of Electrical Engineering, Aug 2011-Dec 2013

Electrical and Computer Engineering, Auburn University, AL, USA. GPA:3.4/4.0 Core GPA:3.66/4.0

Aug 2006–May 2010

Bachelor of Engineering,

Electrical and Electronics Engineering, Anna University, INDIA. Average: 72/100

Research Work Thesis Advisor: Dr. Vishwani Agrawal

Thesis Title: “A Four-Transistor Level Converter for Dual-Voltage Low-Power Design”

Proposed a four-transistor dual-Vth level converter with 31% to 58% power savings and around 52% delay

reduction over the best 32nm CMOS design available in the literature.

Furthermore, a level converter flip-flop combination performs better than an existing level converting flip-flop.

A single-threshold alternative of the new level converter still remains effective, though over a reduced voltage

range.

Publications

Karthik N. Jayaraman; Agrawal, V.D. “A Four Transistor Level Converter for Dual-Voltage Low-Power Design”

J. Low Power Electronics, VOl. No. 10, No. 4, PP 1-12, Dec. 2014.

Professional Experiences

1/2014 – 09/2014

Auburn University, Volunteer, Al, USA

Worked on a concept to reduce energy per cycle using dual threshold voltage than what is possible with a single

Vth in sub - threshold design, given a nominal value for Vth, we determine an optimal supply voltage VDD, and

an optimal higher Vth.

Auburn University, Teaching Assistant, AL, USA. 08/2012 - 12/2013

Teaching, Grading, and helping students in mathematics and concepts of science.

01/2011 – 07/2011

Cognizant Technology Solutions, Program Analyst Trainee, INDIA.

Developer for a project with Bank of New York Mellon with VB, C, C++ and UNIX unit. Worked in security

management for Market Trading.

Academic Projects

Scan based divider circuit from RTL to GDS II in 180nm technology.

Implemented a 16-bit divider circuit, using Non-Restoring division algorithm in VHDL, followed by flow steps

of RTL design, logic synthesis, static timing analysis (STA) using VITAL models and SDF files, pre-layout

simulation, floor planning, placement and routing, DRC, LVS, circuit extraction, post-layout simulation and scan

testing using tools such as IC station, Calibre and Design Compiler.

High Performance Adder Circuit.

Designed a fastest possible 32-bit adder in 180nm CMOS technology using Kogge-Stone adder algorithm in

Verilog. Compared the clock speed, critical path delay, number of gates of non-optimized and optimized design.

Automatic Test Pattern Generator and Fault Simulator.

Implemented an Automatic Test Pattern Generator (ATPG) using D-Algorithm and a Serial Fault Simulator in C

programming language. Performed a complete stuck at testing for a sub-circuit of 74181 4-bit ALU using the

ATPG and Fault Simulator developed. Finally using reverse simulation, achieved a compact test set with over

45% reduction than the initial test set.

Design of a16-bit RISC 5 Stage MIPS Pipeline Processor.

Designed the single cycle datapath of a CPU using VHDL that will realize the Instruction Set Architecture (ISA)

for a new microprocessor (μP) is designed using RISC design principles, with minimal number of clock cycles

per instruction and verified with test program in DE2 FPGA board using Quartus II.

Equivalence checking of combinational logic using Miter Circuit

Designed a Miter circuit with two 16-bit combinational adders, one optimized for delay and other for area using

180nm technology. Test patterns were generated by Tessent Fast Scan for 100% fault coverage and used these

patterns to verify the adders for logic equivalence. Examined critical path delay, number of test vectors, fault

coverage and number of redundant faults in the two circuits.

Course Work

VLSI Design, CAD of Digital Circuits, Computer Architecture and Design, Advanced VLSI design, Low Power

Electronic Circuits, VLSI Testing, Microelectronic Fabrication and Software Quality Assurance.

Technical Skills

CAD TOOLS: Leonardo Spectrum, DFT Advisor, Fast Scan, Design Complier, Modelsim, Cadence.

HDL: Verilog, VHDL, 8085, 8051 Assembly Languages.

EDA tools and Simulators: HSPICE, Primetime, Pspice, Xilinx, MATLAB.

Programming Languages: C, C++, JAVA, JavaScript, Advanced Java, PHP.

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