Post Job Free
Sign in

Project Design

Location:
Bengaluru, KA, India
Posted:
November 12, 2014

Contact this candidate

Resume:

GOKUL P R

**, ***** **, ******* ********, Bannerghetta Main Road, Bangalore - 560076

Mobile: +919*********. E-mail: *********@*****.***

CAREER OBJECTIVE

To secure a challenging position in a dynamic organization where I can use my technical and organisational

skills for the betterment of the same

EDUCATION

M.Tech VLSI Design (6.76 CGPA) 2012 -2014

Amrita Viswavidyapeetham, Coimbatore

Modules:

CMOS Digital Integrated Circuits, Digital Signal Processing, Solid State Devices and Modelling, Digital

Design, Analog and Mixed signal VLSI Circuits, Low Power VLSI Circuits, Testing of VLSI Circuits, CAD

of VLSI Circuits, Computer Architecture and Processor, Embedded Systems, Soft Computing, CMOS RF

System Design, MEMS.

Projects:

“A Delay efficient Vedic Multiplier using Nikhilam Sutra of Vedic Mathematics”

• The objective of this project was to implement a delay efficient Vedic multiplier using Nikhilam

Sutra of Vedic mathematics for three different base sets. The proposed 8*8 multiplier uses Urdhva

Tiryakbhyam Sutra of Vedic mathematics for internal multiplication and the same is compared with a

Modified Booth’s multiplier in terms of power area and delay.

• The project helped me in detail study of various multiplier architectures and their pros and cons.

Moreover it helped me in improving my skills on Verilog HDL and also gave exposure to various

Synopsys design tools like Design compiler, IC Compiler, Star-RCXT TM, PrimeTime etc.

“An Efficient Multiplier Architecture for Modular multiplication”

• A Square-and-Multiply Algorithm for modular multiplication is implemented for different input bit

lengths and the results is compared with that of an ordinary Montgomery multiplier and a k-partition

method for Montgomery multiplier.

• The concept of modular multiplication and its application in Cryptography has been studied during

the course of the project. Moreover, the concept of Montgomery multiplication and its alternatives

has been dealt with.

B.Tech Electronics and Communication Engineering (70.11%) 2007 - 2011

Mohandas College of Engineering and Technology, Trivandrum

Modules:

Digital Electronics, Electronic Circuits, Electrical Networks, Microprocessors, Digital Signal Processing,

Computer Organization, Electromagnetic Theory, Analog Electronics, VLSI Design, Control Systems,

Microwave and Radio Communication

Projects:

Analysis of different Coding Systems for OFDM based Communication Systems.

• This project focused on the application of various forward error correcting codes like Cyclic codes,

Convolutional codes, Reed-Solomon codes etc. on OFDM technique to improve the performance of

OFDM based communication systems.

Senior Secondary School (76.8%) 2006 - 2007

Sree Narayana Central School, Alappuzha, India

Secondary School (83.5%) 2004 - 2005

Sree Narayana Central School, Alappuzha, India

SKILLS PORTFOLIO

Electronic Design: Competent user of Verilog, Basics of System Verilog

Worked on EDA tools: Synopsys Design Compiler, IC Compiler, Star-

RCXTTM, Primetime, HSPICE, Cadence PSPICE, Xilinx, MAGIC,

MATLAB

Computer languages: Basics of C

Platforms: Linux and Windows. Good knowledge of Microsoft Office Suite.

Assembly language: 8085, 8086 microprocessors and 8051, PIC microcontrollers

PUBLICATIONS

• Published a paper titled “PERFORMANCE COMPARISON OF MULTIPLIERS BASED ON

SQUARE-AND-MULTIPLY AND MONTGOMERY ALGORITHMS” in IEEE International

Conference on Green Computing, Communication and Electrical Engineering, held at Dr. NGP

Institute of technology, Coimbatore on March 6th-8th, 2014.

INTERESTS AND ACHIEVEMENTS

• 2012 GATE Qualifier.

• I have a great passion for sports and have actively represented my college in Cricket, Volleyball,

Badminton and Table tennis Championships.

REFERENCES

Available upon request



Contact this candidate