Engineering Design
Resume:
K.SELVAKKANI
E-mail ID : ************@*****.***
Contact no. : +91-886*******
CAREER OBJECTIVE:
It’s my dream, passion and motto to serve the human race with the knowledge and
experience gained through working with expert professionals and engineers thereby leave a mark
for future generations to follow.
EDUCATIONAL QUALIFICATION:
Board/
Year of
Course University
Institute Passing Percentage
Sri Shakthi Institute of Anna
M.E-VLSI 8.41
Engineering and Technology, University 2014
DESIGN (CGPA)
Coimbatore. Chennai
Anna
Info Institute of Engineering, 8.9
University 2012
B.E-ECE Coimbatore. (CGPA)
Chennai
Vivekananda Vidyalaya
State Board 2008 81.75
Higher Sec. School,
HSC
Oddanchatram.
Manimekalai Elango High
State Board 2006 84.85
School,
SSLC
Devathur, Oddanchatram.
DOMAIN OF INTEREST:
VLSI Verification Methodologies
VLSI Design Techniques
ASIC Design Flow
FPGA Design Flow
Advanced Microprocessors and Microcontroller
Digital Electronics
Testing of VLSI Circuits
SKILLSET:
Programming Languages : C, VHDL, Verilog, SystemVerilog
Verification Methodology : UVM, OVM
FPGA Prototyping : FPGA Design Flow
(Timing Simulation, Synthesis, Debugging using Xilinx
Chipscope)
ASIC Design : Familiar with ASIC Design Flow
Static Timing Analysis (Basic Concept)
EDA Tools : ModelSim, QuestaSim from Mentor Graphics
XILINX ISE 14.2
Cadence Design Suite (Virtuoso, NCSim)
Synopsis (VCS, VERDI)
Tanner Tools
INDUSTRY EXPOSURE:
Intel Technology India Pvt. Ltd. (Intel Labs) Bangalore, India
April–Present, 2014
Intern
Projects:
Functional Coverage bin creations for I2C, SPI, UART, I2S, GPIO, DMA.
Tool: Synopsys-VCS
This assignment is to get 100 percent coverage for all the Peripherals. Cover bins have been
created for all the above peripherals and obtained the maximum coverage.
Populate Coverage in VMM planner and generate a combined coverage report.
Tool: Synopsys-VCS, VMM Planner.
In this assignment, I have populated all the coverage files and annotated those coverage files
using VMM planner.
Coverage Plan and Cover Bin Creations for lHL2 Modules.
Tool: Synopsys-VCS, VMM Planner.
This work is to create cover plan for all the modules in the project based on the functionality and
feature. With those plans cover bins have been created for all the modules.
Writing UVM Block Level Test for PMU.
Tool: Synopsys-VCS.
In this assignment, I have written the block level test for PMU. This test is to check the Power
gating for all the power domains and checking the PMU configuration and status registers at
random delay.
UVM VIP Creation for Display SPI.
Tool: Synopsys – VCS
In this Assignment, I have created a separate VIP for DSPI to display the data from memory to
LCD through AXI interface.
Transmos Technology Coimbatore, India
Intern November (2013)-April (2014)
Projects:
Xilinx FPGA based digital PWM using Xilinx Digital Clock Manager (DCM)
Tool : Menter Graphics (Modelsim), Xilinx 14.2
Kit : FPGA SPARTAN 3E
Designed using Verilog HDL
DCM Generated using CoreGen.
Application for DC Motor Speed Control.
Design and Verification of Synchronous FIFO
Designed using Verilog
Verification using SystemVerilog
UVM Compatible
Inverter Design using Cadence Virtuoso.
COLLEGE PROJECT DETAILS:
High Speed UVM Based Verification IP for Gigabit Ethernet Protocol
Verifies both PHY and MAC designs
Built-in configurable scoreboard to measure data integrity
Supports 1Gb, 10Gb interfaces
UVM compatible
Supports SystemVerilog
College Attendance Management System Using Smart Card with Mobile Alert.
PUBLICATIONS AND CONFERENCES:
Survey on “VLSI Verification Methodologies with focus on UVM based
verification”.
Selvakkani K and Mr.Venkatesan K, “High Speed UVM Based Verification IP for
Gigabit Ethernet Protocol”, An International journal of Engineering Research and
Technology (IJERT), Vol. 2, Issue 12, December 2013, ISSN:2278 0181.(ISO
3297:2007)
Selvakkani K and Mr.Venkatesan K, “High Speed UVM Based Verification IP for
Gigabit Ethernet Protocol”, in 1st International Conference on Advanced
Computing & Communication Systems (ICACCS’13), RVS Faculty of Engineering,
Coimbatore.
CO-CURRICULAR ACTIVITIES:
Won the third prize for paper presentation in Info Institute of Engineering, Coimbatore.
Presented a paper entitled “Illegal Usage of Electricity”, a National Level Technical
Symposium held on 24.09.2010 in Jerusalem Collage of Engineering, Chennai.
Presented a paper entitled “Smart Car Parking System “a National Level Technical
Symposium and Project Design Contest in Bannari Amman Institute of Technology,
Sathyamangalam.
Attended One Day Workshop on “VLSI Based System Design & Advancements in
Wireless Communication and Mobile Technology” Organized by Info Institute of
Engineering Coimbatore.
Participated in Two Days Workshop on “SOLID STATE DEVICE MODELING AND
SIMULATION” Organized by KPR Institute of Engineering and technology Coimbatore.
ACADEMIC ACHIEVEMENTS:
Received the ACADEMIC AWARD (2010-2011), Info Institute of Engineering,
Coimbatore.
Class topper for sixth semester and Department Second topper for fifth semester.
Received BEST OUTGOING ACHIEVER AWARD (2013-2014), SSIET,
Coimbatore.
EXTRA-CURRICULAR ACTIVITIES:
Attended an In -Plant-training in BSNL during my B.E.
Industrial visit at Kodaikanal FM Station in B.E and Keltron Company in M.E.
Learned PCB Design in “Vasantha Advanced System” Coimbatore.
ROLES AND RESPONSIBILITIES AS A STUDENT:
Organized a National Level Technical Symposium “INFOREA” in B.E.
Active work and Contributions in “Students Club” and “Rotract Club” Association.
Organized a National Level Workshop “Essentials of FPGA Design and Rapid
Prototyping with Xilinx FPGA”.
PERSONAL TRAITS:
Hardworking
Self confidence
Quick Learner
Team Spirit
PERSONAL DETAILS:
Father’s Name : A.Kuppusamy
Gender : Female
Date of Birth : 11.09.1990
Nationality : Indian
Marital Status : Single
Blood Group : O +ve
Address : K.N.Store,
Devathur,
Oddanchatram,
Dindugal – 624 614.
Linguistics : Tamil, English.
DECLARATION:
I hereby declare the above furnished details are true to the best of my knowledge.
Signature
(K.SELVAKKANI)
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