Project Design

MAHESH KUMAR.G

***********.*@*******.***

Phone: +91-903*******

Objective

To work in a technically challenging environment and serve to the

best of my abilities, contributing towards the growth of the organization.

Education Profile

. Pursuing Masters in VLSI & Embedded System Design from JNTU, Hyderabad

with aggregate of 70% (till now).

. Bachelor of Technology in Electronics & Communication from VNR Vignana

Jyothi Institute of Engineering & Technology, Hyderabad with aggregate of

57%.

. Special diploma in Bio-Medical engineering from Govt.Institute of

Electronics with aggregate of 62%.

. SSC from Little Scholars High School with aggregate of 69%.

Technical Skills

Programming Language : C

Scripting langauges : Python

Hardware Languages : Verilog, system verilog

Operating Systems : Windows & Linux

Tools used : VCS, DESIGN COMPILER, IC COMPILER,

CVER

Area of Interest : Digital & VLSI design

Strengths

. Innovative.

. Hard Working.

. Zeal to Learn New Things.

. Adaptable to any Environment.

Projects

Project- I

. Title: Design & Verification of Zigbee Transmitter (Main Project)

. Description: This is my main project done in my Masters degree. The

aim of the project is to design the physical layer in the Zigbee

protocol. The physical layer consists of four modules. The design is

done in Verilog and verification of the design is done using

SystemVerilog.

Project- II

. Title: Design of Universal Asynchronous Receiver & Transmitter (team

project)

. Description: Designed and implemented Universal Asynchronous Receiver

& Transmitter (UART) controller using Verilog and implemented the

complete ASIC Design Flow. We were the only team to complete the

design with the given specifications and successfully performed gate

level simulations for the same, did P&R using Synopsys IC Compiler.

Project- III

. Title: 4 BIT ALU.

. Description: The aim of the project is to design a 4 bit ALU using

Verilog .The various arithmetic operations algorithms used in

designing the ALU are for addition we used carry look ahead adder, for

subtraction we used borrow look ahead subtractor, for multiplication

we used booth algorithm for division we used sequential division.

Project-IV

. Title: DESIGN OF ASYNCHRONOUS FIFO

. Description: The main aim of the project is to design a ASYNCHRONOUS

FIFO of any size. The design is completed successfully and the

functionality of the design was verified using Verilog.

Personal Details

Father's Name : Vittal.G

Date of Birth : 23-07-1990

Hobbies : Exploring new technologies, playing pc games,

listening to music

Address : S/O Vittal.G

H.NO. :7-5-228/B

Brindavan colony,

Mahabubnagar

Declaration

I hereby declare that the above stated information is true to

the best of my knowledge.

Place:

Date:

(G.Mahesh kumar)

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