Programming Languages: C, C++, Verilog, VHDL

UTKALIKA PANDA

Mobile No.: +917*********/+918*********

E-Mail: ********.*****@*****.***/*****.*********@*****.***

A dynamic Electrical Engineer seeking entry level assignments in “Digital VLSI Architecture Design,

complete VLSI design flow including front-end and back-end for ASIC Implementation and its

verification” with an organization of high repute.

PROFILE SUMMARY

M. Tech. (Microelectronics and VLSI) from Indian Institute of Technology, Hyderabad with 8.48 CGPA

Sound knowledge of Digital VLSI Architecture Design, complete front end and backend flow for ASIC Implementation, and EDA,

CHIP and Digital IC Designs

Currently working at IIT, Hyderabad as a Project Associate on a project based on Cyber Physical System for smarter

health care, funded by Department of Electronics and Information Technology, GOVT. of India

Experience of 2 years in teaching Basic Electronics, Digital Electronics & Signals and Systems at Suddhananda Engineering and

Research Center, Bhubaneswar

Abilities in handling multiple priorities with a bias for action and a genuine interest in personal & professional development

Skill in grasping new technical concepts quickly and utilizing them in productive manner

An effective communicator & analyst with good networking and problem solving skills

EDUCATION

2014 M.Tech. (Microelectronics and VLSI) from Indian Institute of Technology, Hyderabad with CGPA 8. 48

2010 B.Tech. (Electronics & Communication Engineering) from Krupajal Engineering College, Bhubaneswar with

CGPA 7.84

Training attended:

2013 Symphony C Compiler, Design Compiler, and IC Compiler from Synopsys, Hyderabad

WORK EXPERIENCE

Jul’14 to Present Indian Institute Of Technology, Hyderabad as Project Associate

Involved in full chip implementation of a ASIC design from Netlist to GDSII based on Cyber Physical System(CPS) for

smarter health care

Responsible for integration of complete design, creating IO pads, performing synthesis and Static timing analysis (STA)

Jun’10 to May’12 Suddhananda engineering and Research Center, Bhubaneswar as Lecturer

Role:

Lectured on Basic and Digital Electronics and Signals & Systems

Highlights:

Participated in the Internet Of Things(IOT) workshop organized by Indian Institute Of Technology, Hyderabad

Participated in the Cyber Physical System(CPS) workshop organized by Indian Institute Of Technology, Hyderabad

INTERNSHIP

Project: Training on RF Optimization

Organization: BSNL, Bhubaneswar

Duration: May’08 to Jun’08

Description: The internship aimed to gain the practical exposure the challenges in Cellular Network,

understanding the shortcomings in terms of coverage, QoS in the Network and how

to tackle the shortcomings.

Role: Team Member

ACADEMIC PROJECT

Project Title: FPGA Prototype and ASIC Implementation of Low Complex ity and Low Power Architecture

Design for Reduced 3-Lead to Standard 12-Lead ECG Signal Reconstruction Architecture for

Remote Health Care Monitoring

Organization: M. Tech Project for IIT, Hyderabad

Duration: Sep’12 to Jun’14

Platform: Digital/ASIC/FPGA

Description: The project aimed to replace the decade old bulky state-of-art ECG machine (comprising of

10 electrode and 12 lead signals) with a cheap and affordable product, to ease the patient

and doctor’s flexibility to check the heart condition. More precisely this project bridges the

gap between the algorithm and the real life implementation of it, by designing a very low

complex (multiplier less) architecture and its hardware implementation on FPGA and ASIC

platform. This will open up a significant opportunity in the development of personalized

health care and remote health monitoring system.

Project Title: Wireless Traffic Jam Controller using Microcontroller

Organization: B.Tech. Project for Krupajal Engineering College, Bhubaneswar

Duration: Feb’10 to May’10

Platform: Wireless Communication

Description: The project aimed to design traffic jam detector and control system that would be

transmitted to control room to indicate traffic jam route in wireless method & also

broadcasted through a FM transmitter by a traffic police so that other vehicles approaching

that point will divert to another route. Transmission of signal to the control room was done

by radio waves using ASK digital data transmission

IT SKILLS

Programming Languages: C, C++, Verilog, VHDL, 8085 & 8051 Assembly Programming, Basic Shell Scripting, Latex

Tools: ModelSim Simulator (Mentor Graphics), RTL Compiler (Cadence), Xilinx ISE (Virtex-7),Design

Compiler (Synopsys), Formality (Synopsys), IC Compiler (Synopsys), MATLAB, Virtuoso

(Cadence), VCS (Synopsys), Linting (Cadence HAL), Chipscope Pro Analyzer (Xillinx)

OS & Microcontroller: Windows XP, Windows 2007, LINUX, ARM Cortex M3 (mbed NXP LPC1768)

PUBLICATION

Contributed in “Personalised System-on-chip for Standard 12-lead Reconstruction from the Reduced 3 -lead System

Targeting Remote Health Care,” 41st Annual International Scientific Conference on Computing in Cardiology (CinC 2014),

Cambridge, Massachisetts, USA, 7-10 September, 2014. (Accepted)

PERSONAL DETAILS

Date of Birth: 07/07/1988

Current Address: Ordnance factory campus, Yeddumailaram, Hyderabad, A.P.

Languages Known: English, Hindi, Odiya and Bengali

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