Design Project

R ESU M E

Name: P.REKHA

Email: ********@*****.***

Mobile:+91-962*******

CAREER OBJECT IVE:

To strive hard and attain a state of fulfillment so as to leave an everlasting mark behind

and be distinct by enthralling performance with determination, devotion and dedication.

EDUCAT IONAL PROF I LE :

YEAR OF AGGREGATE

S.NO COURSE I NST I TUT ION UN I VERSI TY/BOARD

PASSING M ARKS%

KKC institute of

B.Tech 81.73

1 Technology and JNTUA 2013

(ECE)

E ngineering

Nandavanam

In termediate Board of In termediate

j unior College

2 2009 93.1

E ducation

(M.P.C)

Sri Chaitanya Board of Secondary

3 S.S.C 2006 88.8

Concept School E ducation

CERT I F ICAT ION COURSE DETA I LS:

S.NO COURSE I NST I TUT ION DURAT ION

1 In ternship on VLSI Design Globals Technologies 6 Months

COURSE DETA I LS:

• In t roduction to Basic Electronics.

• D igital System Design.

• D igital System Design using VHDL.

• D igital System Design using Verilog.

• RTL Design and Verification.

• About Synthesis,Simulation and Test bench.

• A bout FSM and Memory.

• About Tasks and Functions.

• In t roduction to ASIC Design Flow.

• A bout FPGA Architecture.

• Hands on Major L ive Industry Projects.

TECHN ICAL SKILLS :

• Good Knowledge in D IG ITAL ELECTRON ICS .

• Having hands on experience in C L ANGUAGE.

• Having hands on experience in V ER I LOG RTL,VHDL RTL andTESTBENCH

coding.

• Having hands on experience in SYNTHESIS and S IM U LAT ION of coding.

• Having good knowledge in ASIC DESIGN FLOW .

• Good knowledge in F LOOR P LANN I NG analysis.

• Good knowledge in P LACEMENT and R OUT I NG concepts.

• Good knowledge in P HYSICAL VER I F ICAT ION analysis.

• Having good knowledge in P CB l ayout and E M I/E MC analysis.

PROJECTS HANDELED :

Title : DESIGN OF H IG H SPEED SQUAR ING CIRCU I T USING

V ED ICM ULT I PL I ER

Platform : V HDL,Xilinx 14.2

Project description:

In this project, a new multiplier and square architecture proposed is based on algorithm of

ancient Indian Vedic Mathematics, for low power and high speed applications. I t is based on

generating all partial products and their sums in one step. The design implementation is

described in both at gate level and high level RTL code (behavioral level) using VHDL

H ardware Description Language. The design code is tested using VHDL Simulator. The

code is synthesized in Synopsys FPGA Express using: Xilinx, Family: Spartan Svq300,

Speed Grade: -6.

R esponsibilities:

• Analyze and prepare design documents.

• Prepared synthesis report.

• Involving in each stage of project development.

• Developing the RTL coding using VHDL.

Title : DESIGN OF D IG ITAL ALARM CLOCK

Platform : Verilog,Xilinx 14.2

Project description

Digital clocks are a clock that displays t ime digitally. They are commonly used as

s top watches to determine the exact t ime used in a particular activity. Unlike analog clocks,

w hich use hour and minute hands to point to the correct time, digital clocks display the

current t ime as numbers. These machines can be implemented in different ways by using

m icrocontroller and FPGA board. Because FPGA based digital clock give fast response and

uses less power than the microcontroller based digital clock. The proposed algorithm is

i mplemented in VERILOG and simulated using Xilinx tool.

Title : DESIGN OF AMBA BASED VECTORED I N TERRUPT CONTROLLER

Platform : Verilog,Xilinx 14.2

Project description:

The VIC provides a software interface to the inter rupt system. In a system with an

i nterrupt controller, software must determine the source that is requesting service and

w here i ts service routine is loaded. A VIC does both of these in hardware. I t supplies the

s tarting address, or vector address, of the service routine corresponding to the highest

p riority requesting interrupt source. The design implementation is described in both at gate

level and high level RTL code using VERILOG Hardware Description Language. The design

code is tested using VERILOG simulator in Xilinx Tool.

ACH IEVE MENTS :

• Topper in 10th class at School level.

• Topper in 12th class at college level.

• Awarded with " The best volunteer " in cultural carnival.

STRENGTHS :

• Hard work, Confidence, Dedication, Honesty.

• Quick reflexes of mind.

• Ability to interact & establish sound relationship with colleagues.

• Effective functioning whether individually or as a team.

P ERSONAL PROF I LE:

Name : P.REKHA

Fathers Name : P.REDDEPPA REDDY

Date of Bir th : 23-06-1991

Language Known : E NGLISH, TELUGU

Mari tal Status : S INGLE

Nationality : I ND IAN

Gender : F EMALE

DECLARAT ION:

I hereby declare that the information furnished above is t rue to the best of my knowledge.

Date:

P lace: Bangalore

S IGNATURE

P.REKHA

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