Design Computer Science

RESUME

ROHIT KUMAR Email ID: **********@*****.***

Mobile: +91-991*******

S/o Satyendra Kumar Sinha

#*, *.*.*.*.C Colony

Adri lane, Boring Road

Patna 800013, Bihar

Objective

To be a Professional at most admired organization to exercise & enrich my technical skills and

contribute the best in the organization that respects hard work and ensures a consistent growth .

Educational qualification

MASTERS in VLSI Design from Manipal University with CGPA 8.11.

B.E in Electronics & Communication Engineering from Visvesvaraya Technological

University with 67.56%, June 2011.

Publication

Published paper on “Design and Verification of USB 3.0 Link Layer (LTSSM) ” at

International Journal of Computer Science and Information Technologies (IJCSIT), Vol. 5(4),

2014, 4916-4921.

Published paper on “Implementation of USB 3.0 SuperSpeed Physical Layer using

Verilog HDL” at International Journal of Computer Applications (IJCA) 95(24):1-5, June

2014. Published by Foundation of Computer Science, New York, USA.

Projects

1. Design and Verification of USB 3.0 Link Layer (LTSSM)

Description:

Design o f LTSSM state machine of USB 3.0 is done in Verilog HDL. Link Training and

Status State Machine (LTSSM) is a state machine defined for link connectivity and the link

power management. Verification of Design is done using SystemVerilog.

2. Design and Verification of USB 3.0 SuperSpeed Physical Layer

Description:

In this project design of USB 3.0 Physical Layer is done using Verilog HDL and Verification

of design is done using SystemVerilog.

3. Data Transactions on System-on-Chip Bus Using AXI4 Protocol

Description:

This project is based on high performance bus architecture that is on A MBA AXI4

where the codes are in VERILOG and has been executed on XILINX software.

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4. Automated Parking System Using Ultrasonic

Description:

A B.E final year project, where a parking system was designed using 8051 microcontroller .

Technical Skills

HDL: Verilog

HVL: System Verilog

TOOLS: Synopsys VCS, Synopsys Design Compiler, Cadence

Virtuoso, Xilinx ISE Design Suite, Altera Quartus,

BSPICE, MAGIC, MATLAB

PROGRAMMING LANGUAGES: C, C++, Assembly languages (µc 8051, µp 8085)

SCRIPTING LANGUAGES: Shell Scripting, PERL, AWK

PROTOCOLS: UART, AMBA AXI3-AXI4, USB (Basics)

FPGA: Altera (DE1, DE2), Xilinx (Spartan) & Synopsys (Virtex)

OPERATING SYSTEMS: Windows xp/vista/7 & Unix/linux (User Level)

Seminars

Congestion Driven Placement for VLSI Standard Cell Design.

Novel Sleep Transistor Techniques Design.

Design of a Wireless Vision Sensor for Object Tracking In Wireless Vision Sensor

Network.

Extra curricular

Member of Global Wings (Global Academy Of Technology).

Won prize in Inter School Football competition.

Got 153 rank in All India Level Mathematics & Science Test (CIPEL).

Got 367 rank in All India Level English Proficiency & General Knowledge Test (CIPEL).

Personal profile

Father’s Name : Satyendra Kumar Sinha

Date of Birth : 21st June 1988

Sex : Male

Languages Known : Hindi & English

Nationality : Indian

Declaration

I hereby declare that the information furnished above is true to the best of my knowledge.

Place: Bangalore ROHIT KUMAR

Date: July 2014

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