Design Project
Resume:
KANUGANTI RAVI TEJA
***********.***@*****.***
Defense colony, Langar house,
Mobile: +918*********
Hyderabad, Telangana-500008.
CAREER OBJECTIVE
Seeking a position in semiconductor industry by utilizing my skills and abilities that offers professional growth
while being resourceful, innovative and flexible.
EDUCATIONAL QUALIFICATIONS
Course Institution University Period of Aggregate
Study M.Tech(VLSI) Vellore institute of Vellore Institute Of 2013-15 7.74
technology Technology, Vellore
(CGPA)
(till date)
B.Tech (ECE) Joginpally B.R Jawaharlal Nehru 2008-12 73.20
Engineering College, Technological University,
Hyderabad H yderabad
Intermediate Narayana Junior College Board Of Intermediate 2006-08 92.80
(MPC) Education, Andhra Pradesh
Matriculation Kendriya Vidyalaya No.1 Central Board Of Secondary 2005-06 71.60
Golconda Education
TOOLS AND LANGUAGES
Scripting language : PERL
Hardware description language : Verilog-HDL (IEEE Standard 1364-2001)
Pre-layout simulator : NC-launch (Cadence),
ModelSim (Mentor Graphic)
Synthesis tool : RTL-compiler (Cadence), Quartus-II (Altera)
Layout Editor : Virtuoso (Cadence)
Back-end : SOC-Encounter (Cadence)
Electronic circuit package : Tina-TI (Texas-Instruments), Multi-Sim (NI)
Static timing analyzer : Common Timing Engine (Cadence)
Programming Language : C and Data structures
AREA OF INTEREST
ASIC design and Verification
TECHNICAL SKILLS
Thorough knowledge of ASIC physical design concepts from partitioning to GDS-II.
Hands-on experience on Tsmc45nm, Tsmc90nm, and Tsmc180nm technology nodes.
Very much familiar with Timing Verification using Common Timing Engine (Cadence)
Been involved in resolving LVS and DRC related issues and further performing Post-layout simulations
in Assura.
Capable of performing Code-Coverage verification for given specifications.
Ample practice on PERL-automation and Good knowledge of DFT concepts.
PROJECTS
1. DESIGN, IMPLEMENTATION AND CODE-COVERAGE VERIFICATION OF AXI-LITE
TO APB BRIDGE FOR NOC APPLICATIONS
Description: Synchronizing the performance of different IP’s from various vendors using AMBA de-
facto standard bus architecture developed by ARM inc. GDS-II was developed in SOC-Encounter of
Cadence at 180nm technology node using Slow.lib library. Code coverage verification of entire
design was carried out using Checker based methodology in Verilog. Ultimately this project achieved
a code coverage of 73% in NC-launch of Cadence
2. DESIGN AND IMPLEMENTATION OF FLOATING POINT FFT BASED CONVLOUTION
Description: Performing FFT of two individual signals, followed by convolution and then IFFT of
resultant signal with pipelining approach aiming towards reduced power consumption. This project
had undergone entire ASIC design flow. Design was synthesized and GDS-II was developed using
RTL-compiler and SOC-encounter of Cadence respectively at 180nm technology node using Slow.lib
library.
3. DESIGN AND CODE COVERAGE VERIFICATION OF SYNCHRONOUS FIFO-
CONTROLLER
Description: Main objective is to perform code-coverage verification of a black-box for a given
specification. This project achieved a code coverage of 75% in Nc-launch of cadence
4. DESIGN AND IMPLEMENTATION OF VEDIC MULTIPLER AT 45nm
HOBBIES
Reading articles related to semi-conductor industry, playing cricket and watching movies.
PERSONAL SKILLS
Flexible, Hardworking, Self-supervising, Punctual, Negotiation and Good team player.
PERSONAL DETAILS
Nationality : Indian
Date of Birth : 25.04.1991
Marital status : Un-married
Father’s name : K. Sudhakar
Languages known : English, Hindi and Telugu
DECLARATION
I hereby declare that the above information and particulars are true and correct to the best of my
knowledge and belief.
Place: Vellore
Date: 31-10-2014 (K.RAVI TEJA)
Contact this candidate