Zhenwei Cai

(***) ***- **** acgi5n@r.postjobfree.com

*** ********* ***, *** ****, CA, 95136

Education

Oregon State University, Corvallis, OR

Master of Engineering in Electrical Engineering June, 2014

JiNan University, JiNan, China

Bachelor of Engineering in Electric Engineering June, 2010

Technical Skills

- Languages: Verilog HDL, C, C++, Java, Bash Shell, SPICE, SQL

- Software: GX developer, STEP7, VisionScape, Matrox Imaging Library, MATLAB, ModelSim, Cadence Allegro, Hspice,

Altera Quartus II, Java Eclipse, LTspice, Photoshop, Microsoft Office

- Systems: Linux (Ubuntu, CentOS), Mac OS X, Windows

- Research: Analog and Digital Signal Processing, PLC, ASICs, FPGA

Work Experience

Project Leader: Oregon State University, Interest Project (2013)

- Intelligent sorting system, PLC design

- Used vision sensor to differentiate black/white balls then sorted them aromatically

Team Member: JiNan University, National Electronic Design Competition (2009)

- Used digital camera to collect road’s information

- Designed and executed the signal processing of sense system and central control system of the smart car model

- Developed spirits of cooperation, patience, perseverance

Project Leader: JiNan University, "Higher Education Cup"National Mathematical Contest in Modeling (2008)

- Won the Second prize of Shandong Province

- Put forward main model of Digital Camera Positioning, wrote paper

- Programmed for the step - determining any point in spatial location’s coordinates with the pictures

Summer Intern: Sifang Rolling Stock Research Institute CO., LTD (2007)

- Tested and maintained Gateway which were used in high-speed EMU (Electric Multiple Unit)

- Assisted in the design of signal control system of 250km/h CHR (China High-speed Railways)

- Programmed experimental chip

- Soldered circuit board which were used in the Remote Control and Communication System

Course Work

Standard-cell ASICs design:

- Programmed a LED based reflector applying standard cell ASIC design flow via Verilog

- Implemented Elucid’s GCD algorithm, 11 opcodes ALU circuits and 8-bit wide and 8 byte deep FIFO via Verilog

- Simulated single-Cycle MIPS and enhanced with additional instructions via Verilog

Analog design:

- Designed a audio amplifier with adjustable gain. USB powered, discrete components only

- Simulated and soldered

- Finished PCB

Multimedia design:

- Principle study about JPEG compression mechanism and running simulation by programming via Matlab

Digital communication system design:

- Error performance of coherent BPSK in a time-varying frequency flat Rayleigh fading channel with convolutional encoding and

block interleaving

Phase-lock loop receiver design:

- Demodulated the transmitted FM waveform and assess system performance via Simulink

Linear system design:

- Designed a linearized model of inverted pendulum on a cart for full state feedback controller and state estimator via Matlab

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