RESUME

SUNIL KUMAR MISHRA

+91-741*******

M.Tech (VLSI Design)

acgcux@r.postjobfree.com

National Institute of Technology, Nagpur

CAREER OBJECTIVE:

To pursue a career in Semiconductor industry, where opportunities exist for innovation, knowledge

enhancement, and professional growth and to utilize my technical skills to the best possible benefit of the organization

I serve.

WORK EXPERIENCE:

1 year Teaching Assistant work in VNIT, Nagpur.

Taken Digital IC design lab using VHDL and Verilog HDL of M.Tech 1st year students.

Taken Instrumentation Lab of B.Tech 4th sem students in VNIT, Nagpur.

14 months of work experience in GTL Limited as BTS site engineer.

Job profile: BTS Site Engineer for Alcatel Lucent BTS.

Location: Odisha and Chhattisgarh

ACADEMIC QUALIFICATION:

Qualification Specialisation College/University Aggregate Year of Passing

M.Tech VLSI Design National Institute OF Technology, Nagpur 6.77 2014

ECE B.P.U.T, Odisha 6.82 2009

B.Tech

XII / PU PCMB Ispat College, Rourkela 54 % 2004

X / SSLC - Saraswati Vidya Mandir, Rourkela 74 % 2002

PAPER PUBLICATION:

Sunil Kumar Mishra et al “FPGA Implementation of Single Precision Floating Point Multiplier using High Speed

Compressors”, International Journal of Soft Computing and Engineering, Volume-4, May2014, 18-23.

Link: http://www.ijsce.org/attachments/File/v4i2/B2180054214.pdf

TECHNICAL SKILLS:

Programming Languages Verilog HDL, VHDL,C, C++

Xilinx – ISE Design Suite

Tools

Mentor Graphics – ModelSim, Eldo

Cadence - IFV

Mathworks – MatLab

Synopsys – Sentaurus TCAD

Devices FPGA:

Xilinx –Virtex-II Pro, Spartan-3E, Virtex-7, Kintex-7

Operating Systems Linux (Ubuntu, Red hat), Windows XP /7

Good Understanding in FPGA Implementation of digital circuit.

Synthesis and Static Timing Analysis

PROJECTS:

M.TECH (MAJOR PROJECT):

FPGA implementation of Kalman Filter:

A fourth order Kalman filter was implemented in Verilog. This Filter was designed to track moving objects

for application like Radar tracking. Data-path & Control path was designed for implementation of Kalman Filter. In

this implementation for reducing hardware requirement Time-Sharing and pipelining is used. Finally the realization

was done on FPGA board.

CHALLENGES FACED:

Reduction in hardware resource requirement.

Maintaining less number of clock cycle for getting output.

HDL LANGUAGE : VERILOG

TOOL : Xilinx ISE 14.6, ModelSim SE 6.2c

FPGA BOARD : Virtex-7

MINI PROJECTS:

I. Verification of Vending Machine:

Controller for Vending machine was designed in Verilog. For verification PSL Properties were written and

verified by using Incisive Formal Verifier (IFV) tool. Finally code coverage is calculated by using ModelSim.

HDL LANGUAGE : VERILOG

TOOL : Incisive Formal Verifier (IFV), Xilinx ISE 14.2, ModelSim SE 6.2c

II. FPGA implementation of Digital Clock:

A real time Digital clock was implemented in VHDL. Asynchronous excess-3 counter was used for

data-path implementation. Finally realization was done on Spartan-3E and Virtex-7 FPGA board.

HDL LANGUAGE : VHDL

TOOL : Xilinx ISE 14.2, ModelSim SE 6.2c

FPGA BOARD : Spartan 3E, Virtex-7

B.TECH PROJECT:

PC based Oscilloscope:

This PC based oscilloscope is designed by interfacing a computer through the parallel port. The input signal is

sampled, stored and plotted on the screen. This is done using a database for storing the sampled data and a web

browser for displaying waveform.

PERSONAL DETAILS:

19th April, 1987 Sri Bhagyalaxmi PG, 4th main, Madiwala, Bangalore-560068.

English, Hindi and Odia https://www.linkedin.com/pub/sunil-kumar-mishra

I do hereby declare that all the particulars made above are true to the best of my knowledge and belief.

D ate :

P lace : B angalore ( SUNIL KUMAR MISHRA )

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