Asic Physical Design Engineer

Location:

Bengaluru, KA, India

Posted:

October 11, 2014

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Resume:

RESUME

Manochitra.M

Email : ********@*****.***

Mobile: +91-952*******

OBJECTIVE

To make a sound position in corporate world and work enthusiastically in team to

achieve goal of the organization with devotion and hard work.

EDUCATIONAL QUALIFICATIONS:-

Degree Board/University Year of completion Marks B.E Noorul Islam college of 2011

(ECE) Engineering, Nagercoil

81.2%

H.S.C Subbiah vidhyalayam girls'

2007 93.4%

higher Secondary

School,Tuticorin.

S.S.L.C Subbiah vidhyalayam girls'

2005 94.8%

Higher Secondary

School,Tuticorin.

Career Summary

Physical Design Engineer from SEP 2011 to Oct 2014.

WORK EXPERIENCE

Analog Team

Physical Design Engineer -3 years 1 month (sep 2011 to Oct 2014)

Arasan Vinayan Technology P.Ltd, Tuticorin- TN-628008.

TOOLS and TECHNOLOGIES

Physical Design Tool : Encounter (Cadence)

Synthesis Tool : RC (Cadence)

Tool Scripting : encounter Tcl (Cadence encounter)

Layout Design Tool :Virtuoso(Cadence)

Scripting Language : Perl and Tcl

Verification Tools : Calibre ( LVS, DRC)

Static Timing Analysis : ETS (Cadence)

Process Technology : 40nm, 45nm, 65nm, 90nm,180nm .

Skill Set

• Physical Design Techniques

Block Level :

synthesized various HDL.

Fix setup/hold violations under MMMC analysis.

Placement of std. cells using instance grouping.

Power, ground structure finalization and power figure derivation for a

given area.

Routing with optimization

Buffer insertion on feed through paths

Knowledge in placement of I/O pads,macros,power and ground

structures during floor plan.

Placement of standard cells in the allocated region,placement of I/O

pins.

Knowledge in reducing slack by up sizing, down sizing and inserting

buffers in ETS.

Hierarchy Level :

Floorplan for Integration of multiple blocks

Buffer Insertion for critical paths.

Diode Insertion to fix antenna violations.

DRC, LVS checks using Calibre.

Testchip Level :

Floorplan and pad ordering.

Analog Buffer insertion or Digital Buffer insertion based on requirements.

Bondpad placement.

DRC, LVS checks using calibre.

Additional Techniques

Knows layout drawing in Virtuoso.

knows to clear LVS and DRC in virtuoso tool.

Drawn various layout analog and digital blocks in virtuoso tool.

PROJECTS (arranged from present to the past)

PHYSICAL DESIGN PROJECT

1.Physical Design and verification for USB for AMS

Technology : 180nm

Foundry : HK_H18

Customers : AMS

Number of clocks

and frequencies : 2(550 MHz)

Voltage : 1.2V

Design size : 450 X 450 um

Project duration : 2 months

2.Physical Design and verification for USB for TI

Technology : 40nm

Foundry : tsmcN40

Customers : IKANOS

Number of clocks

and frequencies : 2(550 MHz)

Voltage : 1.1V

Design size : 143 X 135 um

Project duration : 2 months

3.Physical Design and verification for DPHY for CP, Pixel work

Technology : 40nm

Foundry : tsmcn40, tsmcn40lpedram

Customers : CP(compound photonics), Pixel work

Number of clocks

and frequencies : 2(750 MHz)

Voltage : 1.1V

Design size : 250 X 200 um

Project duration : 2 months

4.Physical Design and verification for DPHY for Sony

Technology : 65nm

Foundry : umc

Customers : sony (MPRO)

Number of clocks

and frequencies : 2(500MHz)

Voltage : 1.2V,1.1V

Design size : 500 X 150 um

Project duration : 2 months

5.Physical Design and verification for Integration block circuit for TX in CP

Tool Used : encounter

Technology : 40nm

Foundry : tsmcn40

Customers : CP(compound photonics)

Number of clocks

and frequencies : 2(300 MHz)

Voltage : 1.1V

Logic hierarchy : Top block Integration with standard cells

Design size : 480 X 1675 um

shape : Rectilinear shape

Project duration : 3 months

6.Physical Design and verification for DFE for RX in CP

Tool Used : encounter

Technology : 90nm

Foundry : CMOS090

Customers : CP(compound photonics)

Number of clocks

and frequencies : 2(350 MHz)

Voltage : 1.2V

Logic hierarchy : block level

Design size : 395 X 200 um

Project duration : 2 months

7. Physical Design and verification for ONFI padring in TSMC TESTCHIP

Tool Used : Cadence virtuoso

Technology : 40nm

Foundry : tsmcn40

Customers : TSMC

Number of clocks

and frequencies : one(200 MHz)

Voltage : 1. 1V

Logic hierarchy : Top block and pad integration

Applied the Physical design skill set mentioned under the skill set summary

Type of pads : mixture of analog and digital pads

Buffers added : Analog buffers for every 100 um

Design size : 2478 x 1741 um

Project duration : 3 months

8. Physical Design and verification for MUX block in TSMC TESTCHIP

Technology : 40nm

Foundry : tsmcn40

Customers : TSMC

Number of clocks

and frequencies : NIL

Voltage : 1.1 V

Logic hierarchy : block

Applied the Physical design skill set mentioned under the skill set summary

Design size : 80 X 80 um

Project duration : 1 month

9. Physical Design and verification for MPHY PADRING in SAMSUNG TESTCHIP

Technology : 40nm

Foundry : l4lp

Customers : SAMSUNG

Number of clocks

and frequencies : one(50 MHz)

Voltage : 1.2 V

Logic hierarchy : Top block integration

Applied the Physical design skill set mentioned under the skill set summary

Design size : 3450 X 3090 um

No of pads : mixture of analog and digital pads

Buffers added : Digital buffers for every 150 um

No of blocks : 2 blocks

Project duration : 3 months

10. Physical Design and verification for 32 bit DAC

Technology : 180nm

Foundry : sbc18hx

Customers : Vinchip

Number of clocks

and frequencies : one(45 MHz)

Voltage & Power : 1.6V & 0.03 x 10-9(W)

Logic hierarchy : block

Applied the Physical design skill set mentioned under the skill set summary

Design size : 450 X 430 um

Project duration : 2 months

11. Physical Design and verification for DPHY

Technology : 130nm

Foundry : SMIC

Customers : Kingway

Number of clocks

and frequencies : 13 clocks(500 MHz)

Voltage & Power : 1.2 V & 0.02 x 10-9(W)

Logic hierarchy : block

Applied the Physical design skill set mentioned under the skill set summary

Design size : 700 X 300 um

Project duration : 1 month

12. Physical Design and verification for ONFI

Technology : 40nm

Foundry : tsmcN40

Customers : Arasan Chip Systems

Number of clocks

and frequencies : 3 clocks(50 MHz)

Voltage & Power : 1.2 V & 0.005 x 10-9(W)

Logic hierarchy : block

Applied the Physical design skill set mentioned under the skill set summary

Design size : 80 X 50 um

Project duration : 2 months

13. Physical Design and verification for I2C block in DPHY

Technology : 40nm

Foundry : tsmcN40

Customers : TI

Number of clocks

and frequencies : one(50 MHz)

Voltage & Power : 1.2 V & 0.003X 10-9 (W)

Logic hierarchy : block

Applied the Physical design skill set mentioned under the skill set summary

Design size : 300 X 60 um

Project duration :1 month

Training Project :- quicklogic & qualcom

1. Technology : 65nm

Foundry : TSMC

Customers : QUCIKLOGIC

Frequency : 500MHz

Voltage : 1.2V

Design size : 202 x 170 um

2. Technology : 180nm

Foundry : TSMC

Customers : QUALCOM

Frequency : 500MHz

Voltage : 1.2V

Design size : 100 x 480 um

Total Training Duration : 8 months

12. Basic Physical Design training

Study of Physical Design Concepts and Issues

Study of Perl, Tcl and Skill languages

Layout design, verification(DRC,LVS) and post layout extraction for inverters, NAND

gate, NOR gate, buffers

Study and analysis on Physical design and verification of DPHY logic using TSMC 65

nm and TSMC 180 nm.

Personal Details:

Name : MANOCHITRA.M

Father’s name : Madasamy.T

Date of birth : 06.06.1990

Marital status : single

Linguistic ability : English,Tamil

Permanent Address : 57, Meenakshipuram 4th street (east),

Thoothukudi.

DECLARATION

I hereby declare that the above information is true to the best of my knowledge and

belief.

Date:

Place: M.MANOCHITRA

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