SystemVerilog, UVM, Specman-e, linux, PERL

NIDARSHAN PJ

Email: ******@*****.***

Mobile Number: +91-998*******

Date of birth: 7 March 1991

Address: No 25, 2 nd rd

floor, 14th main, Nagendra Block, BS K 3 Stage, Bangalore 560050

Objective

To become associated with a company where I can utilize my skill and gain further experience, contributing towards the

goal of the company.

Profile Summary

• Experience in developing Digital and A MS verification environment

• Worked on Phy Interface for PCI Express and USB Super Speed Architecture (PIPE) and MIPI MPHY

protocols

• Worked on Functional coverage and Universal Verification Methodology (UVM)

• Worked on A MS setup for MIPI MPHY protocol

• Good knowledge of Verilog RTL coding, SystemVerilog and Specman-e coding

• Good knowledge of Digital Design Concepts

• Good exposure to technology by undergoing additional training in VLSI

• Good working knowledge of Linux, and C programming

Work Experience

• 8 months in Cadence Design Systems as a Consultant Design Engineer

Technical Skills

Languages Verilog, Systemverilog, Specman-e

Scripting Languages PERL, Shell scripting

Methodology Universal Verification Methodology (UVM)

EDA Tools Cadence Incisive, Questa Sim

Academic Credentials

• PG Diploma in VLSI from RV-VLSI Design Center (Specialization in Frontend Verification), Bangalore in

January 2014

• B.E Electronics and communication from Don Bosco Institute of Technology, Visveswaraiah Technological

University in 2013 with an Aggregate of 69%

• 12th The National PU College Department Of Pre-University Education in 2009 with 84%

• 10th Websters High School Karnataka Secondary Education Examination Board in 2007 with 93.28%

Industrial Experience in ASIC Design and Verification

Organization Cadence Design System

Title Consultant Design Engineer

Protocols Phy Interface for PCI Express and USB Super Speed Architecture (PIPE) and MIPI

MPHY

Description The work is to verify RTL design based on a design specification. My role is to make

sure the design can accomplish tasks successfully and check the behavior of the

design for all corner cases, including error scenario and also worked on AMS setup

for the same.

Roles and Responsibilities

RTL Verification :

• Wrote test sequences and test cases according to design specification using constraint random methods

• Developed checkers in order to verify the behavior of design under test

• Wrote coverage groups in order to measure the verification strategy

• Developed Bus Functional Module (BFM) to apply stimulus to the design under test according to

specifications, stimulus was generated using constraint randomization.

• Code and Functional coverage analysis

AMS Verification:

• Development of AMS setup

• Checking DUT behavior with MIN & MAX voltage and temperature

Automation:

• Automated by using Perl scripting to find number of failed test cases with number of DUT error in

regression

• Automated by using Perl scripting the AMS setup

Declaration:

The above information provided by me is true and relevant documents are present to authenticate the same.

NIDARSHAN P J

DATE:

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