Engineer Project

B.Dheeraj Kumar Singh

Mobile: +** – 810-***-****

EMail: **************@*****.***

EXPERIENCE : 1 + years of experience in Design Verification.

AREAS OF EXPERTISE

• Experience in UVM, SystemVerilog & Verilog.

• Developing VIP's architecture flows for re-usability.

• Expertise in writing test cases and developing verification environments in UVM & SV.

• Developing test plans for achieving the functionality.

• Debugging skills for efficient simulation.

• Experience in developing Code & Functional coverage.

• Knowledge in Oops.

• Have basic knowledge in RTL Design.

TECHNICAL SKILLS

• Languages : SystemVerilog, Verilog, C

• Methodology : UVM

• Tools : Questasim & inFACT.

• Platform : Windows, LINUX.

• Protocol : RAPIDIO, APB & AXI bus protocol.

• Interfaces : SPI & Wishbone.

PROJECTS & EXPERIENCE

PROJECT 1 : RAPIDIO VIP

Company : SMARTPLAY Technologies Pvt. Ltd.

Role : Verification Engineer

Team size :3

Methodology : UVM

Tool : Questasim

Duration : 4 Months (August 2014 to December 2014)

Contribution :

• Developed the UVM environment for Transport layer for driving packets.

• Developed the RAL model for accessing the core registers set of RapidIO.

• Generated the assertions to validate the RapidIO architecture behaviour.

PROJECT 2 : AXI INTERCONNECT

Company : SMARTPLAY Technologies Pvt. Ltd.

Role : Verification Engineer

Team size :3

Methodology : UVM

Tool : Questasim

Duration : 4 Months (April-mid 2014 to August 2014)

Contribution :

• Generated the calculative part for slave transactions.

• Developed sequences for test cases to capture maximum functionality.

• Implemented the coverage report to check the data integrity.

• Developed featured test cases like Read write, Atomic, aligned and unaligned

transactions and involved in its debugging part.

PROJECT 3 : CONTENT ADDRESSABLE MEMORY (CAM)

Company : CVC Pvt. Ltd.

Role : Verification Engineer

Team size :2

Methodology : UVM

Tool : Questasim

Duration : 3 Months (December 2013 to February 2014)

Contribution :

• Developed a verification plan for CAM.

• Developed a SystemVerilog based RTL.

• Generated the test bench environment in UVM

• Involved in the Test Case Development for Error Debugging.

• Involved in developing the coverage closure to verify the functionality.

PROJECT 4 : WISHBONE INTERFACING WITH SPI

Company : CVC Pvt. Ltd.

Role : Verification Engineer

Team size :2

Language : System Verilog

Tool : Questasim

Duration : 3 Months (August 2013 to October 2013)

Contribution :

• Developed the test plan for the wishbone interfacing with SPI.

• Generated the test bench environment in SystemVerilog.

• Involved in test case development and error debugging.

• Developed coverage metrics to achieve efficient functional coverage.

STRENGTHS

• Good Analytical Skills.

• Perseverance and fast learning ability.

• Capable of coming up with no of solutions for a problem raised.

• Self-motivated and Enthusiastic about learning new concepts in emerging technology.

• Has the motivation to take independent responsibility as well as ability to contribute &

be a productive team member.

EDUCATION

• Trained from CVC PVT LTD for 9 months on Front End Design Verification.

• Secured 72% in B. Tech (ECE) from JNTU K, 2013.

• Acquired 88% in 12th from Board of Intermediate Education, 2009.

• Obtained 81% in 10th from Board of Secondary School Education, 2007.

Contact this candidate