VLSI Front-End Design Verification Engineering

NAVNAT H JAGTAP

Mobile: +91-844******* E-mail: acg8n0@r.postjobfree.com

C AREER OBJECT I VE

To produce outstanding results for my organization by applying my skills

and aptitude which I have acquired throughout my career, and thereby

ensure growth of my organization and further enhance my professional

g rowth.

PROFESSIONAL QUAL I F ICAT IONS

1. Maven Silicon Certified Advanced V LS I Design and Verification

course

M aven Silicon VLSI Design and Training Center, Bangalore

J uly 2014 – Jan 2015

2. Bachelor of Engineering, Dnyanganga college of Engineering &

R esearch, Pune

Pune University, Maharashtra, India

Discipline: Electronics & Telecommunication Engineering.

Percentage: 65.94

Year: May 2014

3. H igher Seconda ry, Pu randar Junior College, Saswad

Pune Board, Maharashtra

Percentage: 66.83

Year: 2010

4. Seconda ry School Certificate, Shri Bhairavnath Vidyalaya Vanpuri,Saswad

Maharashtra

Percentage:85.53%

Year:2008

V LS I DO MA I N SK I L LS

Name Description

HDL Verilog

H VL System Verilog

Scripting PERL

L anguage

EDA Tool Questasim and ISE

Verification Coverage Driven Verification,Assertion Based Verification –

Methodology SVA

TB Methodology: UVM

Domain ASIC/FPGA front-end Design and Verification

Knowledge RTL Coding, FSM based design, Simulation, Code Coverage,

F unctional Coverage, Synthesis

OT H ER TEC H N ICAL SK I L LS

Programming Language: Embedded ‘C’

Application software : AVR Studio,Multisim, PCB Artist,Progisp

ACH I EVE M E N TS

Secured 1st Position in I ndian Robotics Championship held at I I T Powai

Secured 2nd position in P roject Exhibition held at B COER Pune

Secured 3rd p lace in M agneto event held at I I T Powai

Secured 3rd position in C ircuit Design held at B COER Pune,

Secured 3rd p lace in Q uick Ci rcuit Ma k ing held a t J SP M Wagholi

Participated in I n te rnational Robotics Challenge at I I T Powai

P ROJECTS

A ] V LS I P roject:

Router – RT L design and Verification

HDL: Verilog

HVL: SystemVerilog

T B Methodology: UVM

E DA Tools: Questasim and ISE

Description : The router accepts the packet on input port and based on the

destination address i t routes to one of the client network among client-

1,client-2,client-3 and client-4 respectively.

Responsibilities:

• Architected the design

• Implemented RTL using Verilog HDL

• Verified the RTL model using Verilog and UVM

• Generated functional and code coverage for the RTL verification sign-

off

• Synthesized the design

SP I Controller Core - Verification

H VL: SystemVerilog

TB Methodology: UVM

EDA Tools: Questasim

Description : The SPI IP core provides serial communication capabili ties with

external device of variable length of t ransfer word. This core can be

configured to connect with 32 slaves.

Responsibilities:

• Architected the class based verification environment in UVM

• Verified the RTL module using System Verilog

• Generated functional and code coverage for the RTL verification sign-

off

B] B.E P rojects:

Swa rm I n telligence in Robotics:

E DA Tools:

• AVR Studio 4

• Progisp

Description :

A team of decentralized Robots has been made who are able to

communicate with each other via Wireless communication. On boundary

t hey do surveillance, whenever any of them will detect an int ruder they will

send their current location to rest of the robots as well as Mi li tary Head-

Quarters and further action will take place.

Responsibili ties:

• Embedded Programming

• Market Survey

Solar Energy T racking System :

EDA Tools:

• AVR Studio 4

• Progisp

Description : A Solar Panel along with LDR sensor has been mounted on DC

Motor. Predefined ini tial position of a panel has set. From the knowledge of

sensor output, panel will be rotating through out the day w.r.t sun and after

t he sun set i t will reset to i ts predefine position.

Responsibilities:

• Embedded Programming

• Market Survey

.

P ERSONAL I N FOR MAT ION

Gender: Male

Language: Marathi,Hindi,English

Permanent Address: A/P: Vanpuri, Tal: Purandar, Dist: Pune, Pin no:412

301

Local Address: Ti rumala PG,Room no 18,#10 &11,Arekere Main

Road,Bannerghatta Road,Bangalore-76

I hereby declare that the information provided here is complete and correct to the

best of my knowledge and belief.

Place: Bangalore Navnath Jagtap

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