Verification Engineer

KIRUTHIKA C

Email : *********.***@*****.***

Tel : +91-961*******

Career Objective:

To seek a challenging career and growth oriented position in the field of

Verification and working on challenging projects in line with my skills and

abilities, enabling professional growth while being resourceful,

innovative, flexible and true team member.

Technical Skills:

Operating Systems - Linux, Windows 98/XP

Verification Language - VHDL and System

Verilog

Scripting Language - familiar with PERL

Protocol Knowledge - AXI, APB, 10 GbE MAC, XAUI and CAN

Methodologies - VMM and UVM

Tools - Questa Sim, Model Sim, VCS and Visio

Version Management - SVN

Academic Credentials:

Bachelors - B. E in Electrical & Electronics Engineering with 82.2%. (2008-

2012) from SSN College of Engineering (affiliated to Anna University,

Chennai, Tamil Nadu).

Job Profile: 2.5 years of professional experience as VLSI Verification

Engineer

0. Currently working with TATA ELXSI Ltd, Bangalore as VLSI-

Verification Engineer (July, 2012 - till date)

Professional Expertise:

Currently working in SOC project which uses UVM Methodology for

verification and handling USB Module.

Project Name : RS-CAN-FD (RTG) Feb,

2014 - Nov, 2014

Brief Project Description:

Project aims at modelling of CHI Model for CAN-FD Protocol, which in

turn consists of TX (Transmission) Handler, RX (Reception) Handler, Memory

Model, Memory Monitor, Mode Handler and PE (Protocol Engine) Handler. The

DUT registers are updated through RAL (Register Abstraction Layer) model.

The TX Handler transmits either CAN Frame or CAN-FD Frame through reference

model to the CAN bus. The RX Handler receives the Frames from the bus and

after filtering mechanism it decides whether to accept the Frame or to

discard the Frame. Various kinds of Memory locations like Message Buffers

and Fifo's are used for Transmission and Reception of Frames.

Role and Responsibilities:

0. Owned the modelling of TX Handler and Mode Handler.

Unit testing of various modules to check the functionality.

Coding of Cover Groups as per the Coverage Plan.

Coding of Scenarios as per the Stimulus plan.

0. Writing of Medium and Advance random Test Cases as per the Test Plan.

Analysis of Cover Groups and holes.

Team Size : 9

Operating System : Linux

Language Used : System Verilog

Methodology : VMM (Verification Methodology Manual)

Tool Used : VCS

Project Name : RS-CAN-FD (DSIM Activity) July,

2013 - Feb, 2014

Role and Responsibilities:

Writing of basic Test Cases according to the Test Plan.

Coding of assertions as per the Checker Plan.

Ensured proper integration of various modules and debugged the failure test

cases.

Found bugs in the design.

Analysis of Assertion Coverage and holes.

Team Size : 5

Operating System : Linux

Language Used : System Verilog

Methodology : VMM (Verification Methodology Manual)

Tool Used : VCS

Project Name : NAVA Nov, 2012 -

June, 2013

Brief Project Description:

Project aims at 16x20 MIMO technologies. The Digital section includes

Thin MAC FPGA, Transmitter (TX) FPGA, Receiver (RX) FPGA, Power and Reset

Circuitry, CPLD, LCD & Keypad Interface, 10GbE Interface and UART

Interface. The FPGAs will process ~2.8 Gbps of Downlink and Uplink data

streams. The data transmission and reception are as follows:-

0. The IP core (10GbE MAC and XAUI) will generate IP packets and it is

fed to THIN MAC (TX) FPGA.

0. THIN MAC (TX) module will process the IP packets and convert it into

THIN MAC packets.

0. THIN MAC packets are given as input to Transmitter FPGA at certain

interval of time.

0. After various stages of modulation Transmission FPGA will transmit the

data (packets) in the antenna.

0. The Receiver FPGA will receive the data (packets) from the antenna,

after various stages of demodulation the data (packets) are fed to

THIN MAC (RX) FPGA.

0. THIN MAC FPGA will check for CRC Error, loss of packets, error in the

data present in the packets and etc.

Role and Responsibilities:

0. Owned verification of Transmitter FPGA and THIN MAC FPGA modules.

0. Identified Verification features and prepared Verification Design

Documents.

Identified the test cases and developed the test plan.

Identified the corner cases and wrote various kinds of test cases to check

the functionality for various features of THIN MAC as per 10GbE MAC and

XAUI specification to achieve functional coverage goals.

Ensured proper RTL integration.

Injected various kinds of errors to THIN MAC and Transmission FPGA to check

its functionality.

Wrote Perl script to validate the results and coverage estimation.

Found bugs in the design.

Team Size : 4

Operating System : Windows XP & Linux

Language Used : VHDL

Tools Used : Model Sim & Questa Sim.

Personal Traits

0. Dedication and Commitment for work

0. Hard Worker, Adaptable, Willingness to learn

0. Good Communication Skills

0. Team Worker

Personal Details

Date of Birth : 3rd December, 1990

Father's Name : K.M. Chandren

Languages known : English & Tamil

Nationality : Indian

Marital Status : Single

Address : 310, Thiruchengode Road, Near Ware House,

Namakkal - 637001,Tamil Nadu.

I hereby declare that all the information provided is true to the best of

my knowledge

Kiruthika

Bangalore

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