Design System

S UB HA LAX M I SAHOO

#*/**, *** **** ****, *st Stage

A rakere Mico Lay-out E mail: acg7qh@r.postjobfree.com

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Mob : +91-906*******/ 779-***-****

Bangalore-560076

Career Objective

Seeking a challenging opportuni ty with an organization which recognizes and utilizes my t rue

potential and permits me to learn new technologies, languages and programming paradigms

w hile nurtu ring analytical and technical skills in the field ASIC front-end verification and to keep

myself updated with the cutting edge technologies.

S umma ry of Qualification

Good understanding of the ASIC and FPGA design f low.

Hands-on experience in wri ting RTL models in Verilog HD L and Test benches in System

Verilog and UVM.

Very good knowledge in verification methodologies.

Experience in using industry standard EDA tools for the front-end design and verification.

V LS I Domain Skills

H D L’s: Verilog

HVL: System Verilog

TB Methodologies: U VM

Verification Methodologies: Coverage Driven Verification

Knowledge: RTL Coding, Simulation, Code Coverage, Functional Coverage,

Synthesis, Static Timing Analysis.

Scripting : Perl at basic level

E DA Tools: H ands on experience on QuestaSim, and Xilinx ISE.

P rofessional Qualification

M aven Silicon Certified Advanced VLS I Design and Verification course from

M aven Silicon VLSI Design and Training Centre, Bangalore

A pril 2014 – Oct 2014

Batchelor of Technology, G andhi I nstitute For Technological Advancement,

B hubaneswar, Orissa.

Discipline: Electronics & communication engineering

CGPA : 8.12

Year : J uly 2013

+2 Science (Chse 10+2) Ramadevi Womens Junior College, Bhubaneswar, O rissa

Council of H igher Secondary Education, Orissa

Percentage: 59%

Year : M ay 2008

Class 10th, Nayahat H igh School, Nayahat, Pu r i

Board of Secondary Education, Orissa

Percentage: 84%

Year : J une 2006

T raining / I n te rnships:

Maven Silicon VLSI Design and Training Centre, Bangalore

Organisatio

n:

Duration: f rom 9 April’14 to t ill now

Undergone Maven Silicon Certified Advanced VLSI Design and Verification course

Description:

Organisatio RTTC[Regional Telecom Training Centre], Bhubaneswar

n:

Duration: 1 Months (from 7 May’12 to 6 June’12)

Description: Undergone Vocational Training on Advanced Telecom

O rganisatio CTTC [Central Tool room and Training Centre], Bhubaneswar

n:

Duration: 1 Months (from 1 August’11 to 30 August’11)

Description: VLSI Design

V LS I P rojects

B asic AMBA Advance Extensible I n te rface (AX I4) P rotocol I n te rface

H VL : System Verilog

M ETHODOLOGY : U VM

E DA Tools : Questa – Verification Platform

D ESCRIPTION : The AMBA AXI protocol is targeted at high-performance, high-frequency

system

design and include number of features that make i t suitable for high-speed submicron

i nterconnects.

T he AXI protocol includes optional extensions that cover signalling for low-power operation.

Verified the protocol using Verilog HDL

Architected the class based verification environment using system Verilog and UVM

methodology.

Generated the functional coverage and code coverage.

D esign & Verification of SPI:

The SPI Controller Core is an interface between wishbone compatible Master Device and SPI

i nterface Slave device. I t supports variable length of t ransfer word. I t supports data latching

and data t ransfer at both edges of clock. This core can be configured to connect with 8 slaves.

T he SPI clock frequency can be adjusted by configuring desirable value in 32 bit clock divider

register. The SPI Core RTL is technology independent and fully synthesizable.

Role: U nderstanding the Architecture and functionality of each module & fix the bugs.

Challenges: U nderstanding the concept of System In tegration, RTL coding and

Verification.

Implementation Details: Verification environment is created using UVM methodology in

system Verilog.

R outer 1x3 – RT L design and Verification:

HVL : System Verilog

EDA Tools : Modelsim, Questa – Verification Platform and ISE

DESCRIPTION : The router accepts data packets on a single 8-bit port called data and

routes the

Packets to one of the three output channels, channel0, channel1 and channel2

Architected the design and described the functionality using Verilog HD L.Verilog

Architected the class based verification environment using system verilog.

Verified the RTL model using System Verilog and UVM.

Generated functional and code coverage for the RTL verification sign-off.

Synthesized the design

Dual Port RA M – Verification:

HVL : System Verilog

EDA Tools : Modelsim, Questa – Verification Platform and ISE

Implemented the Dual Port Ram using Verilog HD L independently

Architected the class based verification environment using system Verilog

Verified the RTL module using System Verilog

Generated functional and code coverage for the RTL verification sign-off

Engineering P roject:

Z IGBEE Enabled Wireless Hotel Menu Order Using Touch Screen And Glcd

Description : A im of the ‘Zigbee enabled menu order in hotel’ design is to develop a

p rototype of a system based on Embedded micro controller(PIC16) which is used for ordering in

hotel using touch screen and graphical LCD. Also in the other end a graphical interface is

designed for taking the orders from different tables and to give the confi rmation .

Seminar:

Presented a seminar on: - “CHANNEL I NTEREFERENCE I N WI- FI”

Description: There a re many different channels defined in the IEEE 802.11 standard.

However, the performance of Wi-Fi networks still greatly suffers from the interference between

users, even if they are using different channels. Here some theoretical analysis of the

i nterference between two channels is done. We show that there is indeed serious interference

between two non-overlapping channels if they are close to each other. Here the CCI and ACI are

d iscussed as well as the PSD of the t ransmit ted signal.

E XTRA-CURR ICU LAR ACT I V I T I ES & ACH I E VE M E N TS:

Selected in District Level Science Olympiad

Topper Of the NRTS exam in the Rayagada District,Odisha

Awarded in various In terschool Level Cultural & Sports Competitions

PERSONAL PROF I L E:

: 28th Nov. 1990

Date of Bir th

Father’s Name : P rabin Kumar Sahoo

Mother’s Name : Kunjalata Sahoo

Nationality : I ndian

Gender : Female

Strengths : H ard working, Self Confidence, Positive Atti tude and My Determination

Languages Known : E nglish, H indi, Odiya

Mari tal Status : Single

Hobbies : Reading, Blogging, Browsing net

D eclaration:

Here by I declare that the information which is given here are correct to best of my

k nowledge and I will be responsible for any discrepancy .

D ATE : 21/11/2014

P LACE : B angalore

S ubhalaxmi Sahoo

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