Analog Layout Engineer

RESUME

Email id: ****.*******@*****.***,

Phone: +91-852*******.

CAREER OBJECTIVE

Seeking a challenging position as a Layout Engineer in a dynamic organization where

innovation, education and sense of ownership are valued and encouraged.

WORK EXPERIENCE:

• Working as a Layout Engineer in Shastra Micro System, Hyderabad.

• Worked as a Design Engineer at Data Point Info Solutions, Hyderabad Since

November -2012 to October 2013.

WORK OUTLINE:

VLSI Fundamentals, CMOS Basics, latch up issues, Floor Planning, Placement and Routing,

Analog Layout, matching techniques, Cadence virtuoso tool editor, deep sub micron

technologies issues, tape out knowledge.

SUMMARY:

Hands on 2 year of experience in layout design and verification on cadence virtuoso tool. Also

Experience in TOP LEVEL ROUTING, TAPEOUT knowledge, Good knowledge in matching

techniques (Inter digitization, common centroid), latch up issues, antenna effects, power

management techniques, PCELL creation

EDUCATIONAL QUALIFICATION:

• Bachelor of Technology in Electronics & Communication Engineering from K.B. R

Engg College, JNTU,Hyderabad in the year 2008- 12 with an aggregate of 81.30% .

• Board of Intermediate Education in MPC from Sri Krishnavani Junior College,Hyderabad in the year 2006-08 with an aggregate of 81.3%.

• Board of Secondary Education from Prathidha High School, yellareddy peta (vi),

Karimnagar in the year 2005-06 with an aggregate of 85 %.

PROFESSIONAL TRAINING:

Undergone intensive training in CUSTOM LAYOUT from Institute of Silicon Systems Pvt

Ltd., Hyderabad for 3 months.

Programming Languages

• Exposure to C, Perl, Tcl programming.

Cadence Tools:

Experience in Custom layout designing of different technology using cadence tools.

• Cadence Virtuoso layout editor-floor planning and routing

• Assura verification-DRC & LVS.

• Technology: TSMC 130nm, 45nm,

Global Foundry 180nm, 130nm.

SOME OF HANDLED BLOCKS:

Project 1: Phase Lock loop (PLL)

Description: PLL is support to generate the required Frequency

Targeted Technology: TSMC 45nm

Role: Develop layout from Schematic, floor plan, Power management, clean DRC and LVS

Challenges: Minimum Poly Routing, Current Densities (EM), matching, shielding.

Project 2: Digital to Analog Convertor (DAC)

Description: It is Circuit to Convert the Digital to Analog

Targeted Technology: TSMC 45nm

Role: Develop layout from Schematic, floor plan, Power management, clean DRC and LVS

Challenges: Minimum Poly Routing, Match the Current Mirrors and Resistors.

Project 3: Op-Amp

Description: It is Amplify the difference Voltage.

Targeted Technology: TSMC 130nm

Role: Develop layout from Schematic, floor plan, Power management, clean DRC and LVS

Challenges: Minimum Poly Routing, Match the Current Mirrors and differential Pair.

Project 4: Band gap reference circuit

Description: It is generate a Voltage that is insensitive to variation in temperature.

Targeted Technology: TSMC 130nm.

Role: Develop layout from Schematic, floor plan, Power management, clean DRC and LVS

Challenges: Minimum Poly Routing, Better Matching.

Project 5: Level Shifter.

Description: It is a Compact Device since it is used as chip Voltage level shifting.

Targeted Technology: TSMC 130nm.

Role: Develop layout from Schematic, floor plan, Power management, clean DRC and LVS

Challenges: Minimum Poly Routing.

DIGITAL LAYOUT PROJECTS:

Project 1: STANDARD CELLS LAYOUT DESIGNING

Tools : Virtuoso Layout XL,L Editor, Assura Verification(DRC,LVS)

Cells designed : INVERTER NAND

AND NOR

OR OAI

MUX D-flip flop

Targeted technology : TSMC 130nm

Role : Drawing the stick diagram from spice net list and to develop

the layout and verifying DRC and LVS.

Challenges : Maintain cell height as constant as 3.69,

Maintain prboundary width in multiples of contact pitch (0.34)

and delivering the project on time.

Skills reached:

• Knowledge on device matching, latch up effects,

• Understanding signal flow to acquire an optimum floor plan and power plan,

• Solving the problems on Deep sub micron techniques,

• Providing shielding for critical signals,

• Following anteena rules,

• Knowledge on deep sub micron effect,

• Solving the DRC/LVS issues,

• Experience on L, XL Editor.

• To level routing,

Under graduate Project Details:

Project Title: DESIGN AND SIMULATION OF CAN PROTOCAL

Tool Used: Modelsim

Role: Team Leader

Description: Controller Area Network (CAN) is a serial network that was originally designed for the

automotive industry, but has also become a popular bus in industrial automation as well as other

applications.

I hereby declare that the information furnished above is true to the best of my knowledge.

Date:

Place: Hyderabad (Y.VENU)

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