Project Design

Ravi Chandra Reddy

Mobile no : +918*********

e-mail: acg5sg@r.postjobfree.com

Carrier Objective:

I am an enthusiastic, flexible and self disciplined person, enjoy working in teams and looking for

good opportunities in career.

Work Experience:

At present working as Design Engineer in Marvell India Pvt. Ltd, Bangalore. 9 months as Graduate Technical Intern,

LSI India, R&D India Pvt. Ltd, Bangalore.

Worked on Front-end Verification using the concept of Register Abstraction Layer(RAL).

Total years of Exp: 1 year 1 month

Academic Profile:

Name of the Discipline Institution University/Board Year of CGPA/Percentage

degree Passing

M Tech. VLSI Design VIT University VIT University 2014 7.824

B. E. ECE AMC Engineering Visveswaraya 2012 58.04%

College, Bangalore Technological

University

12th Standard MPC Delta Junior College, Board of 2007 77%

Hyderabad Intermediate,

Andhra Pradesh

10th Standard St Paul’s English ICSE 2005 83.83%

School, Bangalore

Skill Set:

• EDA Tools : Xilinx ISE design suite, Model Sim PE, Questasim, Synopsys VCS, Keil, Cadence

Encounter, QCA Designer Tool, LT Spice, Tanner Tools.

• Hardware Description Languages : Verilog.

• Hardware Verification Languages : System-verilog.

• Software Skills : C

• Platforms : UNIX, Windows.

M Tech. main project:

Title: RAL implementation and design debug features.

Description : This project is concerned about the verification of a set of registers.

In RAL, there are three main access types RW, RO and W1C. I have written the test cases for the

sequences which were used to write and read register-wise, field-wise and byte-wise. I have also debugged

the design by finding out where exactly the error occurred.

The tool used was Synopsys VCS

Semister Projects:

Project 1:

Title: Design of FIR filter based on a modified Fast FIR algorithm

Description : This project is concerned about designing a parallel FIR filter in four different ways.

a) Without implementing any algorithm.

b) By applying the concept of poly-phase reduction.

c) By applying the concept of fast FIR algorithm where the number multipliers are reduced at the cost

of increase in the number of adders. Since Multipliers occupy a very large area, the area of the filter

is reduced.

d) By utilising the property of FIR filters in which they have co-efficients that are symmetric in nature.

The total number of multipliers are further reduced and the area of the filter is further reduced.

Finally a comparison is done between all the four types and as the number of taps increase the deviation in

the reduction of the area is more conspicuous.

The simulation and synthesis is done using verilog using Xilinx ISE Designer suite. Team size: 1

Project 2:

Title: Design of a low power floating point computation sharing multiplier used for signal processing

applications.

Description: This project is about a multiplier that has less power dissipation in it compared to the normal

array multiplier. The simulation was done using Xilinx ISE simulator and the power consumption was

checked using cadence. Team size: 1

Project 3:

Title: Design of digital clock

Description: This project is concerned about the digital clock that is both 24-hour format and 12-hour

format. It consists of 4 seven segment LED displays. The two digits on the left side indicate the hours and

the two digits indicate the minutes. It was simulated using Xilinx ISE design suite.

Team size: 1

Project 4:

Title: Design of QCA based adders

Objective : This project is about the design of adders with the help of a concept in Nanotechnology called as

QCA. It was designed in QCA designer tool. Team size: 1

B.E. Project:

Title: Design of Servo-Robotic arm in Alectrono company.

Objective: To design Servo-Robotic arm which consists of a base unit and an arm unit. It moves from one

place to other and it is used to pick and place objects. Team size : 4

Personal Profile:

Date of birth : 4th June, 1989.

Gender : male

Marital status : unmarried

Father’s name : Venkat Reddy

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