High School Power

MOHAN C

S/o C Gajendraiah,

Pathiputtur village,

P athiputtur post,

Vadamalapet mandal, Cell no: - +91-998*******

Chittoor-517551, m ****.***@*****.***

A ndhra Pradesh .

Objective:-

To achieve a bright position in fields of technical side so that I can explore better ways of

doing things and to be a great asset to the company that utilizes my skills in a proper way.

Education:-

Year Of

Course Institution Board/University Percentage

Passing

M.Tech,VLSI Sri Vidyanikthen JNTU Anantapur,

2014 84.06

Engineering College Andhra Pradesh.

JNTU Anantapur,

Vaishnavi Institute of

B.Tech, ECE 2011 65.56

Technology,Tirupati. Andhra Pradesh.

Sri Chaitanya Jr College, Board of Intermediate

Intermediate 2007 83.50

Tirupati. Education, Andhra Pradesh.

Z P High School, Board of Secondary

S.S.C 2005 76.66

Pathiputtur. Education, Andhra Pradesh.

Personal Enhancements:-

Programming in C and verilog HDL .

Technical subjects are Digital Electronics, 8085 Microprocessor & Electronic

Devices, 8051 Micro controller.

Summary:-

Work hard to complete the given task in time.

Good communication skills.

Supported many team activities up to my best.

MOHAN C

S/o C Gajendraiah,

Pathiputtur village,

P athiputtur post, C ell no: - +91-

Vadamalapet mandal, 998-***-****

Chittoor-517551, m ****.***@*****.***

A ndhra Pradesh .

Achievements:-

Participated & won prizes in most of the events conducted with in School and college.

Coordinated and done anchoring for a few events.

Project:-

Title: “Design a low power and high speed CMOS Flash a/d converter”.

The present investigation proposes an efficient low power encoding scheme intended

for a flash analog to digital converter. The designing of a thermometer code to binary code is one

of the challenging issues in the design of a high speed low power flash ADC. An encoder

circuit translates the thermometer code into the intermediate gray code to reduce the effects of

bubble errors. The implementation of the encoder through pseudo NMOS logic is presented. To

maintain the high speed with low power dissipation, CMOS inverter has been used as a

comparator and by adjusting the ratio of channel width and length, the switching threshold of the

CMOS inverter is varied to detect the input analog signal. To maintain the high speed with low

power dissipation, the implementation of the ADC through pseudo NMOS logic. The proposed

ADC is designed using 90nm technology in 1.2 V power supply using HSPICE tool.

Hobbies:-

Playing Cricket and watching news channels.

Started watching English Movies recently.

Declaration:-

I hereby declare that the information furnished above is true and correct to the best of my

knowledge.

Place: Tirupati.

(C.

Date:

Mohan)

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