Project Power

Contact

Tel : +91-727*-***-***, 705*-***-***

E mail : ************.*******@*****.***

RAHUL RAJARAM

CHINCHOLIKAR

M Tech (VLSI & Embedded Systems)

B.E (Electronics& Tele Communication)

Career Objective

To seek the challenging position in esteemed organization that needs innovation, creativity

and dedication which enable me to continue to work in a challenging and fast paced

environment, leveraging my current knowledge and fostering creativity with many learning

opportunities.

Career Summary

Professional with M Tech (VLSI & Embedded Systems) and B.E (Electronics &

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Tele Communication) with first class with distinction

Acquired practical knowledge through various trainings and academic projects.

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Possess mathematical foundation, logical thinking & ability to work in pressure

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situations.

Team player with a quick learning capability.

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Education Summary

Marks

Degree School/College University/Board Year

Aggregate.

M.Tech Alpha College of Visvesvaraya Technological

2014 71.45%

VLSI & ES Engineering, Bangalore University, Belgaum.

B.E. A. G. Patil Institute of

Solapur university 2012 60.98%

ECE technology, Solapur

A D. Joshi College

12th Pune Board 2008 61.83%

Solapur.

Shri Nutan

10th Pune Board 2006 75.73 %

Prashala, Solapur

Areas of interest

• EMBEDDED SYSTEMS

• VLSI DESIGNS

Technical Expertise

Designing & Analysis Tools: Xilinx ISE, MATLAB, LABVIEW, PROTEUS, U VISION

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KEIL, MICROWIND, QCAD DESIGNER.

Language: C, C++, VHDL, VERILOG, EMBEDDED C, ASSEMBLY.

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Operating System: Windows XP/Vista/ 7

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Others: MS Office Tools (Word, Excel, Power point), English typing with 30 WPM

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Industrial Training and Internship

Name Of Company Period Assignment

Rashtriya Chemical 17th January To study & analysis of production process of

and Fertilizer, 2011 03 fertilizer through instrument technology and also

Alibuag. February 2011 baggage packing system through PLC Automation.

SAI TEC Institute and

1 YEAR

Research Centre, VLSI Designs and research in Reversible logic.

2013 2014

Bangalore

Academic Project Summary

1. M.Tech Major Project : FPGA Implementation of Low Power, Reversible Logic Based Vedic

Multiplier for ALU Design

Software XILINX 14.5, MATLAB

Team Size 1 members

Duration JULY 2013 – JUNE 2014

Role Project Member

Responsibilities • Understanding the project requirement specification

• Finding features of Vedic mathematics and Reversible logic.

• Preparation of High Level Design & Implementation

• Preparation of Project status report.

• Review and Rework of the project.

• Involved in sign off with project guide.

Description

Low power multiplier plays important role in Processor, the designing of low power multiplier is

challenging task. Until now how many new designs are proposed, still the user needs an optimized

architecture. Reversible logic and Vedic Mathematics is a key role in this project. The basic reversible gate

such as FG (Feynman Gate), HNG (Haghparast and Navi Gate), PG (Peres Gate), NG (New Gate), BVPPG

and R Gate these gates are designed with parameters. Using Reversible Logic the Power Dissipation

reduced drastically according to. The Reversible Multiplier using Urdhva Tiryakbhyam sutra of Vedic

Mathematics is used for Reduce the power and increase the speed respectively. The aim of this project is to

enhance the performance parameter like Gate count, number of constant input and number of Garbage

outputs. The proposed multiplier and ALU are synthesized and implemented on Spartan 6 –XC6SLX45

board.

2. M.Tech Minor Project: Design of Reversible Full Adder/Subtractor using Microwind

Software MICROWIND

Team Size 1 member

Duration OCT 2012 – JAN 2013

Role Project Member

Responsibilities • Understanding the project requirement specification

• Finding the features of Reversible Logic

• Determine the power requirement and path delay of design

• Preparation of Project status report.

• Review and Rework of the project.

• Involved in sign off with project guide.

Description

Reversible logic has become one of the most promising research areas in the past few decades and has

found its applications in several technologies; such as low power CMOS, Nano computing and optical

computing. Reversible logic gates are widely known to be compatible with future computing technologies

which virtually dissipate zero heat. Adders are fundamental building blocks in many computational units.

For this reason, we have simulated several adder circuits using the reversible gates. This paper implements

a design of Adder/subtractor using reversible logic gates. The first design is an implementation of two’s

complement Adder/subtractor is then applied to design a reversible 4 bit ripple Adder/subtractor. It has

been shown in Microwind tool that the reversible circuits outperform the irreversible circuits in terms of

delay and power dissipation.

3. B.E Major project : Designing of 8 Bit Microprocessor Using VHDL

Software XILINX ISE 13.2

Team Size 4 member

Duration JULY 2011 – JAN 2012

Role Project Member

Responsibilities • Understanding the project requirement specification

• Finding the features of ALU

• Determine path delay of design

• Preparation of Project status report.

• Review and Rework of the project.

• Involved in sign off with project guide.

Description

In this project we are trying to design as 8 bit microprocessor by using VHDL. The microprocessor will be

synthesized in VHDL using Xilinx ISE. Then it will be simulated using ISim and the programs are burn

into FPGA SPARTEN 3 kit. This processor includes ALU, control unit, and clock unit. It performs 8

different operations, four logical and four arithmetic operations. First each block is implemented separately

after that all the components integrated to form the processor model. When the program is burn into FPGA

SPARTEN 3 kit (XC3S400 4PQ208), then the proper results are obtained on kit. After implementing the

design, the synthesis report obtained as the number of slices generated are 14 and the maximum operating

frequency is 69.225 MHz. This project work can be considered as founder step towards building SOC.

A chievements & Activities:

Won 1st prize in Photography Competition in ABHIYUVA 2K12 in A. G. Patil Institute of

Technology. Solapur (27th January 2012).

Won 1st prize in Teacher Day Best Message Contest held by ICFAI UNIVERSITY in A.G. Patil

Institute of Technology. Solapur (5th January 2008).

Extra Curricular Activities:

Participated and Presented a paper titled “FPGA Implementation of Low Power

Reversible Logic Based Vedic multiplier for ALU Design” at the International

Conference on Communication and Computing (ESEVIER) organized by the

Society of Information Processing, Bengaluru, ACE, (12th June 14th June 2014)

India.

Presented and published a national level paper on FPGA Implementation of Low

Power, Reversible Logic Based ALU for DSP Application in NCCVS 2014 at K S

School of Engineering, Bangalore (15th May 2014 )

Participated in workshop on Linux Device drivers on Raspberri Board held by

Alpha college of engineering, Bangalore ( 7th September 2013)

Presented Paper on Advance Engineering in GIS and GPS in ‘AGCreation 2012’

event in A G Patil Institute of Technology, Solapur (27th January 2012)

Participated in ROBOTRYST 2012 for a National Level Robotics Championship

held by Robosapiens Technology Pvt. Ltd at B.M.I.T Solapur with Association of

IIT Kharagpur.(selected for final round) from (12 13 January 2012)

Worked as Volunteer for WORKSHOP ON LABVIEW under (IUCEE) ‘Indo Us

Collaboration for Engineering Education’ from (20th July 2011 to 22th July 2011)

Worked as head for thoughts section of AGglomeration 2K11 college magazine.

(Our college magazine Won 3rd Prize in SRUJANRANG Competition)

Presented Paper On Wireless Communication in ‘Orchitect’11 in Nagesh Karajgi

Orchid College of Engineering and Technology, Solapur.(26th February 2011)

Worked as Volunteer for Science Project Exhibition as Avishkar 2010 under

Solapur University at A .G. Patil Institute of Technology, Solapur (30 th December

2010).

Organized various Technical events and various activities to develop personality

under the event “Tech Know Trans 2k11 Beta versions” in AGPIT, Solapur.

Personal Information

Name : Rahul Rajaram Chincholikar

Date of birth : 15 AUGUST 1991

Gender : Male

Marital status : Single

Local address : #538’ 1st floor 4th cross 8th main Hampinagar,

Vijaynagar 2nd stage, Bangalore-560104

Declaration

I do hereby confirm that the information given in this form is true to the best of my knowledge and belief.

Date:

Rahul Rajaram Chincholikar

Place:

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