Mtech_VLSI_SRAM_Design_Verification
Resume:
RESUME
Ramandeep Kaur
Email: **************@*****.**.** / ************@*****.***
Address: 11A/16 G.F W.E.A Karol Bagh, New Delhi – 110005, India
OBJECTIVE
To work in an organization that will utilize and enhance my skill set in CMOS IC Circuit and RTL
design, FPGA/ASIC design, Memory Design, Embedded Systems and applications.
EDUCATION
Degree Subjects/Branch School/ College Board/University Percentage/CG Qualifying
Attained PA Year
Indraprastha Institute Delhi State 2013-2015
M.Tech VLSI and 9.25 / 10
(Master of of Information Government
Embedded
Technology) Technology(IIITD),
Systems
New Delhi
Guru Tegh Bahadur GGSIPU 2008-2012
B.Tech Electronics and 82.47%
(Bachelor of Institute of
Communication
Technology) Technology, New
Delhi
Senior Maths, Physics, Springdales School, C.B.S.E 2007-2008
83.00%
Secondary Biology, Pusa Road, New
(AISSE) Chemistry Delhi
Higher Science, Maths, Springdales School, C.B.S.E 2005-2006
89.40%
Secondary Social Studies, Pusa Road, New
(AISCE) English, Hindi Delhi
PROFESSIONAL EXPERIENCE/ INTERNSHIP
(July, 14 –June, 15)
ST Microelectronics, Greater Noida, India
Manager: Harsh Rawat Mentor: Dr. Alexander Fell
High Density Dual Port Memory Design by exploring algorithms of Single Port SRAM.
Writing the RTL (Verilog) of Dual port SRAM in Verilog and comparing it to the existing in terms of
Area, Power and Timing in 28nm FDSOI (Fully Depleted Silicon on Chip) technology.
Computer Science Corporation, Noida, India (July, 12 - August, 13)
Manager: Vipul Dhingra Designation: Associate Software Engineer
Main task was to develop, enhance and support C# based applications for Post Office in UK. I was
exposed to Technologies like Silverlight, MVC etc.
Bharat Heavy Electricals Ltd (BHEL, R&D Hyderabad) (June, 11- July, 11)
Manager: C.Joseph Mentor: Amrik Singh
Main task was to implement the Modbus protocol using P89V51RD2 microcontroller. It is an embedded
system project with C coding to communicate between 1 Master and many Slaves.
(June, 10 – July, 10)
National Aviation Company of India Ltd, Delhi
Manager: Jagjit Kaur Bhatia
Industrial training based on study of various Overhaul shops in Air India that included Electrical, Radio
and Instrumental workshops. I was exposed to the basics of how Air Traffic is controlled.
TOOLS & LANGUAGES
Scripting Languages : Perl, TCL, Bash
HDL : VHDL, Verilog HDL, Bluespec System Verilog.
Synthesis Tools : Synopsys Design Compiler
Pre-Layout Simulator : Cadence Virtuoso(Sch.), Cadence NCSIM
Post Layout Simulator : Mentor Graphics Eldo
STA : Synopsys Primetime
Load Balancing Tool : LSF
Tool Kits : Arduino (Atmega 328p), FPGA(Spartan 3E),
RasberryPi (ARM 1176JZF-S)
Programming Tools : Xilinx IDE 13.1, MATLAB
Programming Languages : Embedded C, C/C++, Python, Perl
Processors : 8085, 8086, 8051, ARM
Operating System : Linux(RHEL/Debian), Windows
PROJECTS
Hierarchy of Address Decoding Schemes in SRAM on Power, Area and Speed Benchmarks.
(June, 14 – July, 14)
Guide: Anuj Grover (ST Microelectronics)
Row and Column decoder techniques like Divided Wordline Decoder and various other schemes used in
SRAM were compared on the basis of Memory Access time, metal lines, power consumed etc.
Dimension estimation of an object using Raspberry Pi
(Jan, 14 – May, 14)
Guide: Dr. Alexander Fell (IIIT Delhi)
Image processing in Python was performed on captured image of a colored object to find the edges of
the object and the distance between the maximum edges to find its actual dimensions.
Wireless Weather Sensing using Zigbee Protocol
(Jan, 14 – May, 14)
Guide: Dr. Vivek Bohra (IIIT Delhi)
Zigbee protocol was used to wirelessly transmit weather data and Arduino microcontroller was used to
remotely receive sensor data which can be further used for data logging purposes.
FPGA implementation of a 32 bit MAC (Multiply-Accumulator)
(Aug, 13 – Nov, 13)
Guide: Dr. Sujay Deb (IIIT Delhi)
Design was simulated using Xilinx in Verilog HDL. Multiplication was implemented using Booth
Algorithm and comparisons of Adders, Wallace tree addition, Carry Look Ahead Adder and Shift and
add were analyzed on Synopsys DC for timing, area and power calculation.
Design of 2 stage Opamp with Current Mirror - Miller Compensation
(Aug, 13 – Nov, 13)
Guide: Dr. M.S Hashmi (IIIT Delhi)
Research based project which proposed the operational amplifier design using a current mirror load with
miller compensation simulated on Cadence Virtuoso Schematic for high gain.
Positions of Responsibility
Student Representative for Placement in VLSI and Embedded Systems Branch. (April, 14)
Teaching Assistant for Integrated Electronics and Linear Algebra. (Aug, 13 - Feb, 14)
Part of Women in Engineering IIITD Branch-IEEE Student Member. (Sept, 13 - Feb, 14)
Member of Technical Society of GTBIT (TSG). (Aug, 09 - Dec, 10)
Awards and Achievements
DIRECTOR GENERAL MERIT AWARD for 1st rank in 2011 with cash prize of Rs 5000.
Best Athlete Girl of the year 2010 (5 gold medals in 100m,200m,400m,relay(4*100)).
Winner in various events in GATES (Technical fest of GTBIT) like Inquisitive, Pictionary.
Best All Round Girl of 2007-08(SWARAN SELZ MEMORIAL TROPHY) in school.
Best Sports Girl of the year 2007-08 (NATIONAL SPORTS AUTHORITY) in school.
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