Verification Engineer

NEEHA VARGHESE

Email : ***************@*****.***

Contact No : +91-916*******

OBJECTIVE

Inclination to grow and evolve in the field of semiconductors with an

organization that will fully utilize my technical skills, knowledge

and professional experience.

PROFESSIONAL SUMMARY

. 1.8 years of Experience in ASIC Front End Design Verification.

. M Tech in VLSI Design.

. Interests: Digital logic design, VLSI, ASIC,

. Familiar with Verilog, C, C++ programming.

. Familiar with protocols like I2C, AXI .

TECHNICAL SKILLS

Languages : Verilog, VHDL, System Verilog, C, C++.

OS : UNIX / LINUX, Windows

Tools : VCS, Verdi, Perforce, Xilinx ISE.

Protocols : I2C, AXI

PROFESSIONAL EXPERIENCE

AMD Hyderabad, Design Engineer 2, July 2014 - October 2014

Project 1: UVD in AMD DGPU

Description:

UVD performs decoding of different codec standards- H264, MPEG2, HEVC,

etc... This project is a SOC level project mainly targeting the

verification of interfaces of UVD at SOC.

Responsibilities:

. Worked on bring up of test cases across different categories(

security feature, semaphore, register access) in UVD IP at GNB

level.

. Involved in test plan creation and test case bring up across

different categories at GNB level.

. Worked on toggle coverage analysis.

. Worked on Conformal LEC.

Verification Environment: C++.

Verification Tools: Synopsys VCS/Verdi

Tools for LEC: Cadence encounter (Logical Equivalence Checking )

Project 2: Verification of semaphore for UVD in AMD APU

Responsibilities:

. Was responsible for verification of Semaphore as part of

regression.

Verification Environment: C++.

Verification Tools: Synopsys VCS/Verdi.

AMD Hyderabad, Design Engineer 1, Feb 2013 to July 2014

Project 1: CReST for UVD in AMD APU.

Description:

CReST denotes a methodology to test an IP by loading a test

image into internal memory of IP via test I/O pins and executed

with the intent of exercising the internal logic in the same

manner as the traditional functional testing.

Responsibilities:

. Was responsible for generating the vectors in IP for SOC

level execution.

Verification Environment: C++.

Verification Tools: Synopsys VCS/Verdi.

Project 2: Display Controller in AMD APU.

Description:

The Display Controller Engine implements various

functions associated with audio and video

output from the GPU. It can write the display content of

individual video output and composited

frame back to memory.

Responsibilities:

. Worked on bring up of test cases across different

categories within Display IP as part of regression at IP

level.

. Worked on bring up and modification of test cases involving

low power features - FBC(frame buffer compression),LPT (low

power tiling), stutter for Display IP at GNB level.

. Was involved in RTL simulations, regressed few test cases

and created regression status reports.

Verification Environment: C++.

Verification Tools: Synopsys VCS /Verdi

RECOGNITIONS

. Spot Recognition Award for "Ramp up on power - measurement

flows and successfully executing PTPX power measurements

for DCE both at IP and SOC levels" in AMD (July 2013).

EDUCATION

M. Tech VLSI System Design, JNTUH, 2012. 75%

B. Tech Electronics & Communication Engineering, JNTUH, 2010. 68%

ACADEMIC PROJECTS:

MTECH:

Title : Design of fault Tolerant 32 bit ALU USING BCH

codes

Tools : Xilinx ISE 12.4

Board : Spartan 3 FPGA

Languages : Verilog

Description : The main goal of this work is to overcome the

difficulties of designing a 32- bit ALU that is

robust against many attacks or faults and is

able to correct any 3 bit error in any positions of

it's 32-bit input registers. To achieve this

different fault tolerant techniques are considered.

Responsibilities :

. Design of ALU, BCH ECC code.

. Verifying the results on FPGA Board.

DECLARATION:

I hereby declare that the information furnished above is true to the best

of my knowledge.

Date: October 30, 2014

Place: Hyderabad

Neeha

Varghese

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