Engineer Manager

VLSI Trained Engineer

VIJAY KUMAR R.C.

TECHNICAL SKILLS

Electronic Design

Questasim, Modelsim, Xilinx ISE, MATLAB

Packages

C, OOPS, Verilog, System Verilog

Programming Languages

Spartan 3, Spartan 6

FPGA

Familiar Protocols AMBA 3 APB

Familiar OS Windows, Fedora

PROJECT WORK

1. Design of AMBA 3 APB protocol

Description: APB is part of the AMBA 3 protocol family. APB is low bandwidth and

low performance bus. So, the components requiring lower bandwidth like the

peripheral devices such as UART, Keypad, Timer and PIO (Peripheral Input Output)

devices are connected to the APB. The HDL code of the APB protocol is designed

using Finite State Machine. Verification of the HDL code was done by analysing

simulation waveforms.

HDL: Verilog

Software Tools: Modelsim

2. Diversity Combining Techniques for Reducing Interference in Wireless

Networks

Description: In most of the wireless data communication systems such as LTE and

Wi-Fi, they face some interference which is much stronger than thermal noise. Hence

in order to overcome these effects of interference, we used some diversity combining

techniques such as EGC (Equal Gain Combining), SC (Selection Combining) and

MRC (Maximum Ratio Combining) to reduce such interfere nces in the wireless

networks.

Software Tools: MATLAB

PROFESSIONAL COURSES

I Completed Professional Development program, in VLSI Design and Verification,

from Sandeepani School of VLSI Design.

EDUCATION

Name of University/Board Specialization Year Aggregate

course Pass Out

/degree

B.E. Anna University Electronics & 2014 7.62

Communication

12th Tamil Nadu State Board Maths, Physics, 2010 84.58

Chemistry and

Biology

10th Tamil Nadu - 2008 86.8

Matriculation

ACCOMPLISHMENTS

Won I prize in “Technical Wizard” contest by Student contest 2011 held at

K.L.N. College of Engineering.

Won I prize in “Project Expo” at Techno management symposium organized

by IEEE STB 29561 at Mepco Schlenk Engineering College.

Won I place in “Best Manager” & II place in “Surprise Event” at National

Level Technical S ymposium conducted by Velammal College of Engineering

and Technology.

Participated in Paper Presentation, Quiz, Poster Portrait, Circuit debugging at

various National level technical symposium.

.

PERSONAL DETAILS

Father’s Name Chandran S

D.O.B 28th March 1993

Current Address 101, 5A Main, Mallespalya, New thippasandhra post,

Bangalore – 560075.

Email ID **************@*****.***

Contact No +91 - 997-***-****, +91 - 956-***-****

DECLARATION

I do here by declare that all the above statements are true to the best of my knowledge

and belief.

Place-

Date- Signature of the Candidate

Contact this candidate