Design Assistant

Cirriculum Vitae

Imtiyaz Pasha Shaik Email: ************@*******.***

Mobile: +91-998*******

Career Objective:

To pursue a challenging career in the Field of Education, where I can learn and improve my skills

while achieving the goals of the organization.

Summary of Qualifications:

Good understanding of the ASIC and FPGA design flow.

Experience in writing RTL models in Verilog HDL, VHDL and

Test benches in Verilog and SystemVerilog.

Very good knowledge in verification methodologies.

Experience in using industry standard EDA tools for the front-end design and verification.

Good at Digital Design.

VLSI Domain Skills:

Hardware Description Languages: Verilog and VHDL.

Hardware Verification Language: SystemVerilog.

Verification Methodologies: Coverage Driven Verification, Assertion Based Verification

TB Methodology: OVM.

EDA Tools: ModelSim, Xilinx ISE, Questa, ChipScope and Quartus II.

Domain: ASIC/FPGA Design Flow, Digital Design methodologies

Knowledge: RTL Coding, FSM based design, Simulation, Code Coverage, Functional Coverage, Synthesis,

Embedded systems.

Professional Qualification:

Master of Technology from Nizam Institute of Engineering and Technology, Nalgonda

Affiliated to JNTUH, Hyderabad, India

Specialization: VLSI Systems Design

Percentage: 81.

Year: Nov 2011.

Experience:

Working as Assistant Professor at KV Subba Reddy College of Engineering for Women.

Worked as Assistant Professor at GITAM University (From 2013 Julyto May 2014), Hyderabad

Campus.

Trainee and Intern at, Maven Silicon Soft tech Pvt Ltd (May 2012- Sep 2012), Bangalore.

Worked as Assistant Professor at Ayaan College of Engineering and technology, Moinabad (From

2006 to ’07 and 2008 to ‘10), Hyderabad.

VLSI Projects:

Real Time Clock – RTL design and verification

HDL: Verilog HDL.

HVL: SystemVerilog.

EDA Tools: ModelSim, Questa – Verification Platform and ISE.

Hardware: Xilinx FPGA Spartan 3E Development Board.

Verification Methodology: VMM.

Implemented the Real Time Clock using Verilog HDL independently.

Architected the class based verification environment using SystemVerilog.

Verified the RTL model using SystemVerilog.

Generated functional and code coverage for the RTL verification sign-off.

Synthesized the design.

Dual Port RAM – Verification

HVL: System Verilog HDL.

EDA Tools: ModelSim, Questa – Verification Platform and ISE.

Verification Methodology: VMM.

Implemented the Dual Port Ram using Verilog HDL independently.

Architected the class based verification environment using system Verilog.

Verified the RTL module using System Verilog.

Generated functional and code coverage for the RTL verification sign-off.

SPI Master Core Design and Verification

HDL: Verilog HDL.

HVL: SystemVerilog.

EDA Tools: Xilinx ISE, ChipScope, ModelSim, Questa Verification Platform.

Test Bench Methodology: OVM.

Description:

The SPI Controller Core is an interface between wishbone compatible Master Device and SPI interface

Slave device. It supports variable length of transfer word and the core can be configured for 1 to 32 bit, 64 &

128 bit. It supports data latching and data transfer at both edges of clock. This core can be configured to

connect with 32 slaves. The SPI Clock frequency can be adjusted by configuring desirable value in 32 bit

clock divider register. The SPI Core RTL is technology independent and fully synthesizable.

Architected the class based verification environment using system Verilog.

Verified the RTL module using System Verilog.

Generated functional and code coverage for the RTL verification.

Implemented verification process using OVM Test bench methodology.

Implementation of High density complex RADAR signal emulator for FPGA based

RADAR signal processing test applications

Hardware Description Language: VHDL.

EDA Tools: Xilinx ISE, ModelSim and Chip Scope.

Hardware: Xilinx Spartan 3E Development Board.

Description:

The High Density RADAR Emulator is system developed on Field Programmable Gate Array. This

emulator able to resemble the functionalities of basic RADAR system like generating and transmitting and

receiving echo signals with near real values being observed at Practical RADAR system.

Implemented the RADAR emulator coding using VHDL independently.

Implemented DDS section using Core Generator tool.

Synthesized the design.

Implemented the whole design on Spartan development board to emulate the functional behavior.

Verified the functional output using ChipScope tool.

International Memberships:

Member in Institute of Electrical and Electronics Engineers (IEEE).

Life Member in International Association of Engineers (IAENG), Hong Kong.

International Paper Presentation:

Published Paper titled “High Density Complex RADAR Signal Emulator on FPGA” at

International Conference on Technology and Management (ICTM) 2011, Hyderabad.

I hereby declare that the information furnished above is true to the best of my knowledge.

(Imtiyaz

Pasha S)

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