Design Engineering

K.S. AJIN KUMAR

Ittina Sarva Apartments II,

Hongasandra,Bangalore, Email: ************@*****.***

India – 50068 Mobile: +91-875*******

Summary of Qualifications

Good understanding of the ASIC and FPGA design flow

Experience in writing RTL models in Verilog HDL and

Test benches in SystemVerilog

Very good knowledge in verification methodologies

Experience in using industry standard EDA tools for the front-end design and verification

VLSI Domain Skills

HDLs: Verilog

EDA Tool: Questasim and ISE

Domain: ASIC/FPGA Design Flow, Digital Design methodologies

Knowledge: RTL Coding, FSM based design, Simulation,

Code Coverage, Synthesis,

Static Timing Analysis

Professional Qualification

Maven Silicon Certified Advanced VLSI Design and Verification course

From Maven Silicon VLSI Design and Training Center, Bangalore

Year: October 2014 (pursuing)

Master of Engineering, Anand Institute of Higher Technology, Chennai

Anna University, Tamil Nadu, India

Discipline: VLSI Design

Percentage & year: 73.2 % first Class, June 2014

Bachelor of Engineering, Sree Sastha Institute of Engineering and Technology, Chennai

Anna University, Tamil Nadu, India

Discipline: Electronics & Communication Engineering Percentage

& year: 65.5 % first Class, April 2012

HSC – (Tamil Nadu State Board, March 2008, 85.58% First class)

SSLC- (Matriculation, April 2006, 82.00% First Class)

Achievements

Appreciated and honored for excellence in labs and projects during college days.

Experience

June 2014 – December 2014, Maven Silicon, VLSI Design and Training Center

VLSI Projects

Real Time Clock – RTL design and verification

HDL: Verilog

HVL: SystemVerilog

EDA Tools: Questasim and ISE

Responsibilities:

Implemented the Real Time Clock using Verilog HDL independently

Architected the class based verification environment using SystemVerilog

Verified the RTL model using SystemVerilog.

Generated functional and code coverage for the RTL verification sign-off

Synthesized the design

Router 1x3 – RTL design

HDL: Verilog

EDA Tools: Questasim and ISE

Description: The router accepts data packets on a single 8-bit port called data and routes the packets to

one of the three output channels, channel0, channel1 and channel2.

Responsibilities:

Architected the design

Implemented the RTL using Verilog HDL

Verified the RTL using Verilog HDL

Generated code coverage.

Synthesized the design

Video Graphics Adaptor – RTL Design and Verification

HDL: Verilog

EDATools: Questasim and ISE

Responsibilities:

Architected the design

Implemented the RTL using Verilog HDL

Verified the RTL using Verilog HDL

Implemented the design on the Spartan, Xilinx FPGA and verified the design on the board

Engineering Project

M.E VLSI Design: “Modified Blooms Filter For Genomic Sequence Search Using BLASTN”.

AIM: To accelerate the search speed of DNA database search I have constructed an accelerator based on

similarity search techniques using the Master Scheduling Algorithm. Achieved a speedup around the

magnitude of 13nms. Basic Local Alignment Search Tool for Nucleotide sequence [BLASTN] is used by

NCBR as a sequence analysis tool to find areas of similar regions between database sequence and query

sequence.

TOOL Used: XILINX ISE

Coding Language: Verilog HDL

B.E [ECE]: “Orthogonal Frequency Division Multiplexing using FPGA”.

AIM: To modulate and demodulate the sine wave using the technique of OFDM using Field

Programmable Gate Array and thereby reduce the huge power consumed. The results were the power

being reduced by a factor of 1.5.

TOOL Used: Xilinx ISE, Modelsim

Coding Language: Verilog HDL

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