FPGA Design Engineer

Reza Rezvani

* ***** ******* ****, *******, Ontario L3T 3C2

Phone: +1-416-***-**** Email: ***.*******@*****.***

FPGA Design Engineer

Challenge-driven and highly knowledgeable FPGA Design Engineer offers over a decade of experience in protocol

design and analysis, packet processing, and software hardware interface design in Telecommunication and IT

companies with diverse and geographically remote teams.

Brings expertise in high speed logic design, timing closure, and verification methodologies. Has proven capability

in architecture design, block partitioning, quality and reliability. Possesses strong technical leadership, problem-

solving and debugging skills.

Knowledge Areas:

Altera FPGA families Modelsim Protocols: Ethernet, TCP/IP

Xilinx FPGA families NCSim Processor & Microcontroller

High speed logic design Constrained Random Tests C, Pyhton

SERDES ISE, ChipScope PCIe, Wishbone

Verilog and System Verilog Quartus, Signaltap Board Design

VHDL Scripting languages: TCL, Perl Switching power supply

Timing closure BIST built-in self-test I2C, SMII, SPI

SVN, source version control Signature Analysis DSP & Digital Filters

Simulation Scan based testing Windows, Linux

Professional Experience:

Hewlett-Packard, Singapore, July 2008 to Aug 2014

FPGA Design Engineer

Key Results:

• Designed and developed protocols to communicate status and data between switches using broadcast and

point2point packets. This protocol enabled HP to add stacking capability to HP2900 and HP3800 switch

series.

• Designed and developed 10G packet processor in FPGA in which FPGA receives L2 packets from two 10G

ports, encapsulates in GRE header, and then transmit the GRE packets out. This design provided additional

GRE tunneling capacity for HP switches/routers.

• Prepared a CRT (constrained random test) environment using system verilog to verify 10G packet processor

FPGA. Improved productivity by reducing the total amount of time spent on verification.

• Designed hardware abstraction layer (HAL) in FPGA. Introduced a new protocol that eliminate mutex

implementation in software so all processes in software can use FPGA interface as if it is only dedicated to

that process.

• Two invention disclosures:

o Invented a mechanism to prevent permanent circulation of broadcast packets in a closed network.

o Introduced a new communication protocol between FPGA and microprocessor that fully utilize the

communication bandwidth between FPGA and processor.

• Prepared guideline for FPGA/CPLD programmers included work flow, coding style, release process, version

control, and block reuse.

• Architecture design, block partitioning and software/FPGA partitioning for large complex designs

• Designed and implemented complex logics in FPGA chips for Network Switch Products.

• Designed and implemented fully automated test environment and test cases for each project.

BBS Telecommunication, Singapore, Aug 2005 – July 2008

Hardware Engineer

Key Results:

• Developed single-phase energy meter accuracy class of 1% based on TERIDIAN 71M6521 metering chip.

Design met IEC standard and passed through EMI/EMC tests. This design was 20% cheaper than previous

product of the company.

• Developed power line modem for “CELENEC Band A” based on YiTRAN chip.

• Involved in design and implementation of PABX project which was based on Xilinx Spartan-3

and Blackfin processor.

Niksu Negar Co., Tehran - Iran, Nov 2002 – Aug 2005

FPGA Design Engineer

Key Results:

• Designing and implementing PCIe bus analyzer based on Xilinx Virtex2Pro50 device and its embedded

PowerPC processor. All logic blocks of this product were designed to work at 250MHz clock rate.

• Designing and Implementing PCIe Bus Performance Analyzer based on Xilinx Virtex2Pro50 device. All logic

blocks of this product were designed to work at 250MHz clock rate.

MCT Co., Tehran - Iran, Mar 2000 – Nov 2002

FPGA Firmware Engineer in Software Radio Team

Key Results:

• Design and implementation of a Quad Receive Signal Processor in FPGA for GSM-BTS (Using

Altera’s ACEX and APEX devices).

• Design and Implementation of a two channel GMSK Modulator in FPGA for GSM-BTS (Using Altera’s

ACEX and APEX devices).

• Implemented Viterbi Decoder by TMS320C542 processor.

Other Professional Experiences

• Direction of arrival (DOA) estimation, Beam-forming and implementing in SHARC ADSP-

2160 processor.

• Designing and simulating systolic array architecture for MVDR beam-former and DOA

estimation.

• Designing and implementing a 2KW Voltage Stabilizer.

• Designing and implementing an AC Motor Protector

• A simple DC Motor Controller

Education:

National University of Singapore

Aug. 2006 – Apr.2008, M.Sc. in Management of Technology

Amirkabir University of Technology, Tehran - Iran

Sep. 1996 - Mar. 1999, M.Sc. in Computer Architecture

Thesis Title: “Design and Implementation of Broad-Band DOA (Direction of arrival) Estimating Systems”.

Iran University of Science and Technology, Tehran - Iran

Sep. 1990 - Jan. 1996, B.Sc. In Computer Engineering

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