Engineer System

JOHN- LE

*** **** ***, *** **** Ca *****. Home 408-***-****. Cell 408-***-****

"*********@*****.***"

Objectives:

Having BS-EE, Looking for position as Sr.Engineer Technician, with over

more than 10 yrs. experience in R/D, building prototype and soldering,

testing, troubleshooting PCB, components and system level. With 7 years'

experience in laser (Class IV, certified) alignment Optical and High speed

CCD camera. Also, experience in Semiconductor system (Intel FAB

Lithography) and Applied Material (Semiconductor System)

Professional Experiences:

Spectra-Physics (Santa Clara CA Apr/14 - Current) Contractor.

Sr.Engineer Technician, troubleshooting High Power Supply for laser system

and Laser Diode, debug PCB, testing & calibration, component and System

level, Validation NPI, Supporting R/D, MFG engineer in Electronic, SW

(FPGA), Laser Engineer, Mechanical. High Power Supply for Semiconductor

(Intel, KLA, Apply Material Science), Evaluation ECO, revises procedure,

Refurbish Unit.

Illumina, Hayward. CA. Dec/2007 till Feb/2014

Sr. Engineer Tech. Optical and Laser alignment and System Power Up.

. Optical alignment, mirror, lenses, beam slitter, beam combiner, Powell

lens, Dichotic, Compensator, Objective lens, Projection lens, CCD

Camera (1W), Class IV Laser, (wave length 660 mm and 532 mm), Laser

Alignment less than 2 micron and 2 pixels picture images.

. Electrical, Robotics, XYZ stage, Laser Power Meter, Trouble shooting

Stand Alone Server, System Fluid, Pump, Vacuum, Electrical, trouble

shooting module and component level, Verifying FGPG

. Laser/Electro-Optics, Opto-Mechanics.

. Installation and replaced system hardware and system debug.

. Running and testing FIT (Final Integration Test), Chemistry, Reagent,

NaOH

NVIDIA (Santa Clara, CA) April/2006- June/2006 (Contractor).

QA Engineer, Testing with compatibility & validate GPU and PCI express

Video card, with Dual CPU (Intel, AMD) and high speed Mother Board, using

MS- Kernel debugger. Testing with multiple OS of MS, (Win 2003 Server, XP-

64, and Vista.

Jan/2006 - Apil/2006 (FPGA Class)

Advance Verilog 2001 syntax, Algorithm State Machine (ASM) design of FIFO,

PCI, UART, and Microprocessor. RTL coding, State Machine, set up time, and

register. Project using Altera Quartus II, SW with simulated with Mentor

Graphics ModelSim, and test on prototype board.

Compaq/HP (Fremont, CA) - Sr.Debug Engineer Tech. August/1999-May/2005.

* Validated, Debug Hardware and Firmware DEC Server. Support Design

engineer.

*Technical training for more than 100 International Field Service Engineer.

* Debug, tested DEC modules: CPU, Memory, Power, Clock-Switch, I/O

Controller.

*System test Multiple OS, VMS, and UNIX. Testing functionality and

Reliability,

* Debug, test NSK modules: CPU (dual) and IOC (7 types controller: Fast

Ethernet, ATM, Slam...10/100 Mbs), NSK- Sierra controller.

INTEL (Hillsboro, OR) - Sr. Debug Engineer Tech (Contract). May/97 -

Sept/98.

*Compatibility & Validation Silicon and Debug CPU Pentium II (500MHz) and

Chipset (450 NX, 450GX).Thermal and timing analysis...

*Set up, installation, configuration, debug and build completed server

(Merces) and client (Cisco, Andataco) to test with Multiple O/S through

different Protocol (TCP/IP, NetBios, Token Ring, ATM.). Software: DOS, MS-

window (95, 98, NT, Server), UNIX, Solaris, NetWare, SCO. Tools (ITP, TLA,

and PSMI). Testing Firmware, system BIOS.

Knowledge:

Front End and Back End design Semiconductor as Chip Designer. ASIC, CPU,

and Silicon Debug Engineering and Fabrication MFG.

Software:

FPGA, Boundary Scan, Synopsis Synthesis, Verilog, VHDL (FPGA,

XILINX), CADENCE (OPUS), Mentor Graphic (Vers. 8.4.3.1), Perl, C, C++,

Pascal,

FORTRAN, Assembly Languages. TEK- Spice, UNIX, ABEL, SCHEDIT, Magic, and MS

window (NT, 95, 98, XP, Office).

Computer system: UNIX, SUN (Solaris), Gould, IBM, VAX (VMS).

Hardware:

Laser meter, Digital

Oscilloscope, logic analyzer (Tektronix, HP), Signal generator, function

generator, DMM, Spectrum

Analyzer, Sonet.

System Servers: DEC, Mercess. HP Enterprise.

Education:

2005 Audit student at SJSU in Master of Science in Electrical Engineering.

Jan/2006-Apr/2006-Taking class: Advance Verilog system design (FPGA, CPU,

MEM, FIFO, PCI, and UART).

Jun/2005- Dec/2005-SDI (Certificate- Silicon Drafting Institute) IC -layout

mask design.

In process of working on VLSI-Design-Engineer certificate at UCSC -

(Extension).

Portland-State-University (BS-EE. June/1993).

References: Upon Request

Awards:

1) Found Intel Pentium II bug (Intel, Oregon, 1998).

2) Found Design bug on Alpha Server (DEC). Boston, MA. In 1999.

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