Verilog, VHDL, C, Physical Design, RTL synthesis/Coding

Damarla Paradhasaradhi

D. No: *-***/A, Damarla Vari Thota, Email: ***************@*****.***

Nowluru, Mangalagiri, Guntur, Secondary Email: **************@*******.***

Andhra Pradesh - 522503. Mob: +919*********, +919*********

Career Objective:

Seeking an entry level position in my career where I get handful of work experience and my

technical and interpersonal skills can be used effectively that dynamically work towards success

and the growth of the organization

Academic Credentials:

Completed M. Tech in Electronics Engineering specialized in VLSI Design from Pondicherry

University (A Central University) with 7.64 CGPA in May 2014.

Completed B. Tech in Electronics and Communications Engineering from Vasireddy

Venkatadri Institute of Technology with 71.83% in April 2012.

Completed Intermediate (10+2) in M.P.C from Sri Chaitanya Junior College with 93.60% in

April 2008.

Completed Secondary Education from C. K. High School with 75.33% in April 2006.

Proficient:

Experience in writing RTL Codes, FSM Based Design in Verilog HDL and Test benches in

System Verilog.

Good Understanding of the ASIC and FPGA Design flow and Digital Design.

Worked on the Digital as well as analog and high speed VLSI circuits Designs with Verilog for

logic implementation and Xilinx ISE Tool for Simulation and Synthesis.

Proficient in development of IP level Verification using system Verilog/Verilog/VHDL.

Familiar with ASIC Back end design Methodologies and verification flows.

Software Proficiency:

Operating Systems : Linux, Windows Family

Programming Languages : Verilog HDL, VHDL, C, MATLAB, PERL

Tools : Xilinx ISE 13.1, Microwind, Tanner Tools, Multisim,

Basics of Cadence Virtuoso

Areas of Interest:

Digital Design with Verilog HDL and VHDL

Low Power VLSI design, Digital CMOS Design

ASIC Design, RTL Design

Physical Design and Verification

Achievements:

Certified by Indian Institute of Technology Madras in DSP Programming & Applications.

Participated in AICTE sponsored National Level Seminar on “Mathematical Challenges in

Medical Image Processing” Conducted by Prasad V Potluri Siddhartha Institute of

Technology, Vijayawada.

Attend the Work Shop on “Custom IC Design using Cadence Tools” Conducted by Govt.

Model Engineering College, Kochi.

Participated in The Institute of Engineers India sponsored “Technical Meet-2013” Conducted

by Pondicherry University, Pondicherry.

Attend the Work Shop on “I-Sense robotics” in an International Knowledge Carnival

Conducted by Vellore Institute of Technology, Vellore.

Academic Projects:

1. Title : An Area Efficient Square Root Carry Select Adder

Description : In the design of Integrated Circuits area occupancy plays a vital role

because of increasing the necessity of portable systems. General carry select adder is known

to be fastest adder among the conventional adder structures but the area occupancy is

more. This work uses an efficient carry select adder by sharing the common Boolean logic

(CBL) terms which gives an efficient area compared with general carry select adder.

2. Title : Performance Analysis of Different Multipliers using Square Root Carry

select Adders

Description : In this Project an area efficient square root carry select adder was

designed. That idea is applied to different multiplier structures like Array and Wallace Tree

Multipliers and the performance of these multipliers using regular square root carry select

adder, modified square root carry select adder using BEC logic and proposed square root

carry select adder using CBL logic are observed.

3. Title : A Location Based System for Mobile Devices Using RFID

Description : This is a Prototype Application of Internal Location-Based Service Using

Passive RFID (Radio Frequency Identification) to determine location. The function of the

system is based on strategically located passive RFID tags with exclusive identifiers placed

around buildings which are identified using a RFID reader attached to a PDA or mobile

phones.

Extra Curricular Activities:

Participated in 33km walk on National Youth Day on Jan 12th Vivekananda birth day.

Participated in Blood Donation Camp-2013 organized by HDFC Bank Ltd. & Pondicherry

University.

Participated in Inter-Department Cricket Tournament organized by Department of Physical

Education and Sports in Pondicherry University.

An Active member of Sports club in our college.

Took active participation in organizing events in school and college level.

Strengths:

Tendency to mingle with people and can lead a team when needed.

Hardworking and willingness to learn new concepts readily.

Dedicated towards the assigned works with positive attitude.

Personal Details:

Father’s Name : D. Murahari Siva Sankara Rao

Date of Birth : 31-07-1991

Mother’s Name : D. Uma Maheswari

Gender : Male

Languages known : Telugu, English, Hindi, Tamil, Spanish

Hobbies : Playing cricket, Listening melody music, Photography

Permanent address : D.No:4-413/A, Damarla vari thota, Nowluru [Village],

Mangalgiri [Md], Guntur [Dist], Pin Code: 522503, Andhra

Pradesh, India.

Declaration:

I hereby declare that the information furnished above is true to best of my knowledge.

Place: Guntur

Date: (D.PARADHA SARADHI)

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