Engineer Design
Resume:
Ray Taylor
Summary
An electrical design engineer specializing in
analog and mixed signal circuit design for both
integrated and discrete solutions.
Experience
Boulder, CO
(An innovative hearing aid company specializing in
Bone Conduction Hearing Aids)
Senior Electrical Engineer
Led research and development of higher power
2008 - 2012 processors. Performed manufacturing support
including verification and validation, test fixture
development, product debugging and diagnosis, and
product improvement. Performed board level circuit
design and simulation using LTSpice. Board layout
using PCB Artist.
Black Forest Engineering, LLC
Colorado Springs, CO
(A research and design company specializing in
infrared camera development for the US military)
Senior Design Engineer
Performed pixel circuit design and simulation
verification for 12um pitch focal plane arrays for
US ARMY.
Utilized SmartSpice simulation, Dolphin SMASH
Simulation, LAKER schematic capture, ICEDIT layout,
in 0.18um process.
2006-2008 ON/AMI Semiconductor, CO Design Center Colorado
Springs, CO
(A worldwide company with expertise in Medical ASIC
Development)
Analog Staff Design Engineer
Was project lead on non-invasive medical ASIC for
blood analyses.
Used Cadence tools for simulation and verification
work.
1999-2006 Starkey Labs, CO Research Center Colorado Springs,
CO
(A world renown company in Hearing Aid Development)
Analog Engineer
Designed several key circuits in various CODEC
designs. (1.0v Supply Voltage/ with less than 500uA
supply current for entire chip: Low Jitter
Oscillator/PLL, Telecoil Equalizer with offset
self-trim, Low Noise Microphone Supply Voltage
Reference, Voltage Doubler for external EEPROM,
H-bridge Output Driver, Battery Regulator.)
Team lead on "works first time" chip design.
Used Cadence tools for simulation and verification
1992-1994 IBM
Tucson, AZ
(A world leader in business solutions.)
Design Engineer
Designed motor driver controller chip for tape
drive
Designed Oscillator/Phase lock loop ASIC for tape
drive
Used Cadence tools for simulation and layout
Education
Penn State University State College, PA
B.S., Electrical Engineering.
Graduate level courses taken in Analog and Power
Electronic design from University of Arizona, and
University of Colorado at Colorado Spring.
MEAD courses in Low voltage/Low power analog
design, and Sigma Delta ADC conversion.
Patents
US Patent 5,414,382 "Impedance Buffer for Driving
Capacitive Loads" May 9, 1995
References:
Greg Pauls: 303-***-****
Stephen VanDuyene: 574-***-****
Nick Pergola: 720-***-****
Bill Simms: 303-***-****
Mark Kazmier: 719-***-****
Bill Dittenhofer: 719-***-****
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