M.Tech VLSI for Internship

CURRICULUM VITAE

NAME:KESHAV K L PH:953-***-****

e-mail: ******.****@*****.***

PREFACE & CAREER OBJECTIVE .

I am an Electronics and Communication Engineer pursuing M.Tech in VLSI at VIT University,

completed first year with First class. Currently looking for an internship. Objective is to

implement my knowledge and ideas into VLSI design. To work for progress of the company and

career growth.

TRAININGS

SKILL SET

Verilog level advanced LEAN intermediate

SIX SIGMA basic

XILINX level advanced

FMEA

CadenceVirtuso level intermediate

KAIZEN

PERL level beginner

ESD & MSD

TCL level beginner

EXPERIENCES:

CENTUM ELECTRONICS (SEP 2011 – SEP 2012):

Designation : Trainee Production Engineer.

Work Profile:

Handled ABB –US customer project division with annual turnover of 13 Cr.

Evaluating production targets and achieving them within time and cost parameters.

Handling a project consisting of 60 people. Starting from the assembly process of PCB’s

(PTH process) till finished goods.

Optimizing man and machine utilization to achieve pre set production targets.

Streamlining new process concepts for production optimization, yield improvement and

adopting cost reduction technique.

Mentoring, motivating the team members towards achieving defined goals and objectives

of better productivity.

Brief understanding of the stages of Surface Mount Technology (SMT) process.

Achievements at work:

Increased the efficiency of production by 25%. Reduced one shift man power without

affecting the production quantity and revenue by using the concepts of LEAN.

Reduced the overall component damage from 6% to 2.3%.

YOKOGAWA INDIA LTD ( SEP 2012 – JULY 2013):

Designation: QA Engineer (Analyzer division)

Work Profile:

Certifying Analyzer System (SOx, NOx, CO, Gas Chromatograph, O2) for its

functionality and quality.

Maintaining the database of quality certification documents.

Handling customer inspections and audits.

Perform internal audits of Analyzer division.

Conduct quality circle meeting on monthly basis.

Achievements at work:

Automated customer service feedback form and service request form using ADOBE

Designer Tool. Previously was hand written and mail request.

PROJECT AND RESEARCH ACTIVITY:

Currently working on “ Implementation of Self Optimized Feature Mapping

(SOFM) technique for speech recognition” 3rd Sem 2014.

SOFM is a technique part of neural network which supports self learning mechani sm.

This would be implemented on an hardware which can provide the advantage of precise and

faster recognition rate.

“Implementation of Fast Dynamic Time Warping for speech recognition ”,

[Presented in NCSET Conference organized by VIT University], Chennai May 2014.

The algorithm was implemented using Verilog code. The new algorithm was

implemented to which reduced the complexity to O(n) from O(N2) of the available algorithm.

The hardware implementation produced a fast matching rate with very low power consumption.

ASIC flow was followed using Cadence Virtuoso.

FPGA implementation of Dynamic Time Warping algorithm for speech recognition,

[Presented at SET Conference organized by VIT University ], Chennai November 2013.

The algorithm was implemented using verilog coding. The synthesized code was

implemented on Spartan 3e kit and verified.

“Remote Foot Controller for Dental Workstation” as part of final year thesis 2010.

The main aim of the project is to communicate using IR signal. The project contains two unit that is

transmitter unit and receiver unit. The transmitter unit contains PIC18f252 with LCD display, keypad and

IR LED. The operation to be performed is transmitted by the transmitter

SUBJECTINTERESTS

ASIC, Digital IC Design, IC Technology.

EDUCATION

M.TECH in VLSI (2013 -2015) from VIT University with CGPA of 6.73.

Bachelor of Engineering in Electronics and Communication (2010) from JSS

Academy of Technical Education, with 55.2%.

Pre University in PCMB (2005) from National College, Jayanagar, Bangalore with

65.45%.

10th from St Paul’s English High School, Bangalore (2003) with 71.5%.

ACTIVITIES

Member of IEEE Photonics Society, VIT University.

Won Bronze medal in 3000 mts run at Taluk level. Participated in VTU athletics meet.

Was the team captain of college Shuttle Badminton Team and participated in VTU

Tournaments.

Organized and Coordinated IEEE fest for 2 years.

Coordinated several in campus placements as a placement coordinator.

PERSONAL DETAILS:

Gender : Male

Father : Lakshmikanth.P

Marital status : Single

Date Of Birth : 23.04.1988

Languages known : English, Hindi, Kannada

Declaration: I hereby declare that all the information furnished above is correct to the best of my

knowledge and belief

Place: Bangalore (Keshav K L)

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