VLSI Trained Engineer
Obj***
Lavanya Nimmagadda
TECHNICAL SKILLS
Electronic Design Xilinx ISE, Modelsim,Leonardo Spectrum
Packages
C, Verilog, Vhdl, Basics of System Verilog
Programming Languages
Microcontrollers / FPGA Xilinx FPGA (Sparton 3E)
Familiar Protocols AXI 4 Lite interface
Familiar OS Windows xp/7
WORK EXPERIENCE
Worked as Asst.professor in priyadarshini institute of technology and
Science for women (affiliated to JNTUK) during jun-2009 and nov-2010.
Worked as Asst.Professor in Malineni perumallu Educational society’s group of
institutions(affiliated to JNTUK) during Dec-2011 and june-2013.
PROJECT WORK
1. Title of the Project: AXI-4 LITE Master BFM
Description: The basic objective of this project is building Bus Function model of a
master with AXI-4 Lite interface to check a slave with AXI-4 Lite interface.
Software Tools: Modelsim
Language: Verilog
2.Title of the Project: Memory optimized Dual port TCAM for intrusion detection
Description: The aim of this project is to store a large no of virus patterns in a limited on-
chip memory by sharing storage spaces using an adaptively dividable line.
Software Tools: Xilinx ISE
Language: VHDL
PROFESSIONAL COURSES
I Completed Professional Development program in VLSI Designing from Sandeepani
School of VLSI Design.
EDUCATION
Name of University/Board Specialization Year Aggregate
course Pass Out
/degree
M.Tech JNTUK VLSI Design 2012 72.5%
B.E. ANNA University ECE 2009 71%
12th Board of Intermediate MPC 2005 88.1%
Education
10th Board of Secondary SSC 2004 81.33%
Education
ACCOMPLISHMENTS
Got second rank in seventh class public exams in my class.
Got second rank in elocution conducted at our school.
PERSONAL DETAILS
Father’s Name : Sankara Rao.N
D.O.B : 30-08-1988
Current Address : 6-1, 1 St Main, 2 Nd Cross, Saraswati Nagar,
Mahadevapura, Bengaluru.
Email ID : **********.*******@*****.***
Contact No : 088********,098********
DECLARATION
I do here by declare that all the above statements are true to the best of my knowledge
and belief.
Place- Signature of the Candidate
Date-