Electrical Engineering

Gavin Francis Paes

404-***-****

*****.****@******.***

OBJECTIVE

To secure a full time position that is challenging, facilitates personal growth and contributes towards revolutionizing computer technology through innovation

EDUCATION

Georgia Institute of Technology December 2014

Master of Science, Electrical and Computer Engineering GPA 3.75/4.0

Veermata Jijabai Technological Institute (V.J.T.I), Mumbai, India May 2013

Bachelor of Technology, Electrical Engineering GPA 8.30/10

COURSEWORK

Advanced Computer Architecture

Advanced Memory Systems

Advanced Programming Techniques

Advanced VLSI System Design

Advanced Digital Systems Test

Wireless Networks

Advanced Microarchitecture

Real-Time Systems

Special Problems

TECHNICAL SKILLS

Software Skills: Matlab, Simulink, Cadence Virtuoso, Orcad, IDE MPLAB, Keil

Programming Languages: C, C++, Perl, Verilog, Assembly, Embedded C

PROFESSIONAL EXPERIENCE

Intel Corporation-Oregon, USA (Internship Program-3 months) August 2014

• Individually performed research to demonstrate the potential of stream detection to remedy the performance degradation observed in Intel’s NVMe SSDs caused due to increase in write amplification resulting from pseudo randomization of sequential workloads with in the disk

• Extended an existing SSD simulator to emulate the working of Intel’s NVMe SSD through the incorporation of multithreaded producer-consumer relationship, host I/O request queuing, write stream management as well as implemented a stream detection algorithm and stream handling logic into the simulator to observe the potential reduction in write amplification

• Showcased a reduction in write amplification of approximately 50% using stream detection

Indian Institute of Science-Bangalore, India (Research Intern-2 months) July 2012

• Performed a detailed comparison between real-time scheduling algorithms like the rate monotonic, earliest deadline first and deadline monotonic in order to highlight their individual advantages as well as drawbacks

ACADEMIC PROJECTS

DRAM Memory Scheduling Policy February 2014

• Designed and implemented a new DRAM memory scheduling policy capable of outperforming FR -FCFS, Closepage and Openpage

scheduling policies using the USIMM simulation infrastructure and trace files

Cache Replacement Policy January 2014

• Individually designed and implemented a new cache replacement policy to prevent against trashing and scanning workloads while

simultaneously exploiting workload locality

• Implemented existing state of the art SHIP and DRRIP cache replacement poli cies using the ISCA-2010 Cache Replacement Championship framework

Memory System and Arithmetic Unit Design December 2013

• As part of a group of four, designed and integrated using Cadence virtuoso, the system schematic and layout of a SRAM array,

interconnect and adder system having the capability of writing and reading a set of data to and from the SRAM array, driving the

data through the long interconnect and adding the data to the stored partial sum

• Individually designed the schematic for the column d ecoder, multiplexer of the read/write circuit and the sense amplifier of the read

circuit using Cadence virtuoso and performed layout design of the multiplexer transmission gates satisfying the Design Rule Check(DRC) and Layout Versus Schematic (LVS) tests

Cache Coherence Protocol Simulator December 2013

• Created a simulator using C++ that maintains coherent caches for a 4, 8, and 16 core CMP (Chip Multiprocessor) capable of implementing the MSI, MESI, MOSI, MOESI, and MOESIF protocols for a bus-based broadcast system.

Out of Order Superscalar Processor Simulator November 2013

• Individually simulated an out -of-order superscalar processor in C++ based on the Tomasulo algorithm featuring a dispatch unit,scheduling queue, register file, functional units, a common data bus and a reorder buffer

Real-Time Face Tracker November 2013

• Co-designed a platform independent real -time face tracking camera device using OpenCV’s face detection algorithms for applications in video conferencing to facilitate automatic tracking of a presenter’s movements

PATENT/INVENTION DISCLOSURE

Intel Corporation: Elimination of I/O Intermingling in Virtualized Environments Pending Review

Co-Invented a method to eliminate performance-degrading intermingling of I/O from various Virtual Machines within Solid State Drives

PUBLICATIONS

Priority Driven Scheduling for Real-Time Systems-An Overview

International Conference on Advances in Electrical, Electronics and Computer Science (ICAEECS 2012)

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