Engineering Electrical

Shashank Vishwanath Ahire

Email: ********.******@*****.*** Mobile No: +91-720*******

Objective: To secure a job in VLSI field and get familiar with current technology, thus enhancing my knowledge and

skills and complementing in company’s growth.

Education:

Degree Course Institute Percent/CGPA Year of

Passing

M.Tech VLSI Design VIT 8.3 May-2014

University,Vellore

BE Electronics and Maharashtra Institute 61.7 % May 2010

Telecommunication of Technology, Pune

12th Science Jai Hind 77 % May 2006

Jr.College,Pimpri

10th SSC Shivbhumi Vidyalaya 81.2 % May 2004

Pune

Areas of Interest:

Physical Design

SoC Design

ASIC Design

Digital and Analog systems

FPGA based system Design

Verification.

Tools and Languages:

HDL (Hardware description language):- Verilog.

Scripting languages: - Perl, shell.

Language

Other languages: - Basic of C

Synthesis Tool NClaunch (Cadence)

Pre Layout Simulator NCsim(Cadence), Modelsim (Altera)

Post layout simulation Virtuoso schematic editor,Virtuoso layout suit (Cadence)

Tools

LVS/DRC

STA Encounter RTL compiler(Cadence), NClaunch (Cadence)

Backend SoC encounter (Cadence)

Parasitic Extraction Tools Assura RCX (Cadence)

Publication:

Journal:

“Implementation of Fixed and Floating Point Square Root using Nonrestoring Algorithm on FPGA”

Contributors: Anuja Nanhe, Gaurav Gawali, Shashank Ahire and K. Sivasankaran.

published in International Journal of Computer and Electrical Engineering, Volume 5 Number 5 (Oct. 2013).

Conference:

“ Implementation of Fixed and Floating Point Square Root using Nonrestoring Algorithm on FPGA”

Contributors: Anuja Nanhe, Gaurav Gawali, Shashank Ahire and K.Sivasankaran

published in 5th International Conference of Electronics and Computer Technology (ICECT)-June,2013.

Journal:

"Clock Network Synthesis Based on Dual-MST Algorithm "

Contributors: Shashank Ahire, Anuja Nanhe, Gaurav Gawali and John Reuben.

Published in International Journal of Applied Engineering Research (IJAER),Volume 9 Number 15 (2014)

Journal:

" Implementation of AMBA AHB for On-chip Communication"

Contributors: Shashank Ahire, Anuja Nanhe, Gaurav Gawali and K.Sivasankaran.

accepted for the journal International Journal of Applied Engineering Research (IJAER) and will be published

very soon.

Technical Skills:

Familiar with the ASIC design flow(Front end),SoC design,FPGA design,Static timing analysis(STA),back-end

design, analog design,clock tree synthesis(CTS).

Academic Projects:

May ‘14

On chip switched capacitor based DC-DC converter for low ripple and Fast Response

Design of an on chip DC-DC converter to step down the input voltage with low ripple and fast response

in 90nm technology. Multiple output voltages generated by the converter depends upon input signal frequency.

Main objective of the project is to reduce ripple in output voltage and fast transient response.

Tools used: Cadence virtuoso.

Jan ’13 - May ‘13

Clock Network Synthesis Based on Dual-MST Algorithm

Construction of a symmetric clock tree for ISPD2010 benchmark derived from Intel 45 nm designs using

modified dual-MST geometric algorithm (DMST). In DMST algorithm zero merge skew process and Kruskal’s

algorithm is used to reduce skew and wire length. Elmore delay model is generated for verifying the skew in the

tree.

Tools used: MATLAB, LTspice.

* Selected for oral presentation as one of the best projects in Science, Engineering and Technology Conference 2013

held at VIT University, Vellore.

Jan ’13 - May ‘13

AMBA AHB implementation on FPGA

Implementation of Advanced Microcontroller Bus Architecture (Advanced High Speed Bus) using TSMC

45nm technology. In this project protocol is designed to communicate between two masters and tw o slaves. The

arbiter is designed with fix priority FSM to select a master. Decoder use to select the slave. A FIFO is used as

slave for read and write operation.

Tools used: Cadence NCSIM, RTL Compiler, SoC Encounter.

Sep ’12 - Nov ‘12

Square root implementation on FPGA

Verilog implementation of nonrestoring square root algorithm using Verilog HDL coding on FPGA . In

this project, pipelined architecture is designed to implement 8 bit fixed and floating point square root in Field

Programmable Gate Array (FPGA) using modified non-restoring square root algorithm. This algorithm results in

reduced area in terms of logic elements when compared to restoring algorithm.

Tools Used: Quartus II, ModelSim.

Other Activities:

Participated in B.E projects competition Intexication,2009 in MIT,Pune .

Volunteering for NATIONAL ROBOTIC CONTEST 2009.

Contact this candidate